SiGe Strained Transistor Channel Design
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Solution Overview
Problem
As transistor scaling reaches challenges at 32 nm and 16 nm nodes, existing methods for improving transistor performance through strain induction in channel regions face limitations, particularly in efficiently inducing compressive and tensile strain in PMOS and NMOS transistors without incurring high costs and complexity, such as low-temperature dopant implantation for reducing crystal defects.
Innovation Solution
The formation of compressively strained PMOS and tensilely strained NMOS transistors is achieved by etching specific trenches in the silicon substrate and filling them with SiGe, which induces strain in the channel regions, combined with epitaxial growth of silicon layers to enhance carrier mobility, thereby improving conductivity and reducing power dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature dopant implantation is used to reduce crystal defects, then carrier mobility is improved, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent changes the physical state and temperature parameters of the silicon substrate during implantation. By heating the substrate to elevated temperatures (e.g., 200-400°C) during dopant implantation, the process reduces crystal defects and improves carrier mobility without requiring extremely low temperatures, thereby simplifying the manufacturing process while maintaining reliability improvements
2Productivity
If transistor size is scaled down to improve circuit density, then circuit density increases, but manufacturing precision and device performance deteriorate
Solution Approach 1:
The patent applies localized strain induction in the channel region of the transistor using SiGe source and drain structures. By creating specific compositional gradients and strain fields only in the channel area, the method improves carrier mobility and device performance at scaled dimensions without requiring proportional scaling of the entire device structure, thus maintaining manufacturing precision while achieving high circuit density
3Reliability
If strain inducing layers are deposited to improve carrier mobility, then carrier mobility increases, but device complexity and manufacturing steps increase
Solution Approach 1:
The patent combines the strain induction function with the source and drain region formation into a single integrated structure. The SiGe source and drain regions serve dual purposes: as electrical contacts and as strain-inducing elements for the channel. This merging eliminates the need for separate strain inducing layers and reduces the total number of manufacturing steps while maintaining improved carrier mobility
Solution Approach 2:
The SiGe source and drain structures perform multiple functions simultaneously: they provide electrical connectivity as source/drain regions, induce mechanical strain in the channel to enhance carrier mobility, and serve as part of the transistor active structure. This multi-functionality reduces device complexity by eliminating dedicated strain induction components
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively enhances carrier mobility by up to 20% in PMOS and NMOS transistors, allowing for lower supply voltages and reduced power dissipation, while avoiding costly low-temperature implantation methods that introduce crystal defects.
Implementation Method 1
The strain inducing layers induce either a tensile or compressive strain on the channel region of the transistor, according to the type of the transistor, and in so doing improve carrier mobility in the channel region
Implementation Method 2
epitaxial growth of silicon layers to enhance carrier mobility
Data Source
AI summary
An integrated circuit die includes a silicon substrate. PMOS and NMOS transistors are formed on the silicon substrate. The carrier mobilities of the PMOS and NMOS transistors are increased by introducing tensile stress into the channel regions of the NMOS transistors and compressive stress into the channel regions of the PMOS transistors. Tensile stress is introduced by including a region of SiGe below the channel region of the NMOS transistors. Compressive stress is introduced by including regions of SiGe in the source and drain regions of the PMOS transistors.