Low-Capacitance ESD Diode Junction Doping Compensation
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Solution Overview
Problem
Existing ESD protection devices in semiconductor devices suffer from increased parasitic capacitance due to auto-doping effects at the p-n junctions, which can lead to undesired increases in junction capacitance and affect device performance.
Innovation Solution
The implementation of a semiconductor device design that includes a lightly doped n-type and p-type epitaxial layers with specific dopant distributions across the interface, where n-type dopants are implanted to compensate for the auto-doping effect caused by p-type dopants, thereby maintaining the desired dopant concentrations and reducing capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ESD protection devices are added to protect ICs during ESD events, then reliability is improved, but parasitic capacitance increases
Solution Approach 1:
The patent applies local quality by creating a specific dopant distribution profile at the p-n junction interface, with peak concentrations positioned to minimize capacitance in the critical junction region while maintaining ESD protection functionality throughout the device structure
Solution Approach 2:
The patent changes the dopant concentration parameters by implementing a tailored dopant distribution with specific peak concentrations and positions, rather than using uniform doping, to optimize the balance between ESD protection and capacitance reduction
2Reliability
If dopant concentrations are increased to improve ESD protection, then reliability is improved, but junction capacitance increases
Solution Approach 1:
The patent makes different regions of the epitaxial layer have different dopant concentrations, with peak concentrations localized at specific positions away from the immediate junction interface, providing high ESD protection where needed while maintaining low capacitance at the junction itself
Solution Approach 2:
The patent performs preliminary dopant distribution design during the epitaxial growth process, pre-positioning peak dopant concentrations at optimized locations before device operation to ensure both ESD protection and low capacitance are achieved from the outset
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively mitigates the auto-doping effect, maintaining the desired junction capacitance and ensuring the semiconductor device operates within optimal parameters without compromising other device characteristics such as holding voltage and breakdown voltage.
Implementation Method 1
implanting p-type dopants in a second region of the n-type epitaxial layer
Implementation Method 2
implanting n-type dopants in a first region of the n-type epitaxial layer different than the second region
Implementation Method 3
growing a p-type epitaxial layer over the n-type substrate such that an interface forms between the n-type and p-type epitaxial layers
Data Source
AI summary
Diodes for ESD protection devices are described. The diodes have low capacitance. In an example, a semiconductor device includes a substrate, an n-type epitaxial layer on the n-type substrate in a first region of the n-type substrate, and a p-type epitaxial layer on the n-type epitaxial layer with an interface between the n-type and p-type epitaxial layers. The p-type epitaxial layer has a first concentration of p-type dopants throughout the p-type epitaxial layer. Also, the semiconductor device includes a p-type dopant distribution straddling across the interface, the p-type dopant distribution having a first peak concentration of p-type dopants greater than the first concentration, and an n-type dopant distribution straddling across the interface, the n-type dopant distribution having a second peak concentration of n-type dopants. The second peak concentration is substantially same as the first peak concentration.