ESD Protection Circuit With Insulated Extended Drain Region
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Solution Overview
Problem
Integrated circuit devices are vulnerable to damage from electrostatic discharge (ESD) events due to excessive voltages, which can break down insulating films or cause electrothermal failures, and existing ESD protection circuits often rely on the operation of active transistors, limiting their effectiveness and controllability.
Innovation Solution
A circuit with ESD protection is developed, incorporating a silicon controlled rectifier (SCR) and an extended drain region transistor that diverts charge away from active LDMOS output driver transistors, allowing the trigger voltage of the SCR to be set independently of the protected transistor, and featuring a disconnected or insulated extended drain region to prevent trigger voltage walk-in during multiple ESD events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing ESD protection circuits rely on the operation of active transistors, then the protection mechanism is simple, but the effectiveness and controllability are limited
Solution Approach 1:
The protection circuit is segmented into distinct functional components: an SCR (silicon controlled rectifier) for charge diversion, an extended drain region transistor for voltage triggering, and insulation structures for stability. This segmentation allows each component to perform its specific function optimally, improving overall protection effectiveness while maintaining reasonable complexity
Solution Approach 2:
The patent introduces an SCR as an intermediary device between the ESD event and the active LDMOS transistor. The SCR acts as a controlled charge diversion path, mediating the protection mechanism to achieve better effectiveness and controllability without directly compromising the active transistor
2Reliability
If the extended drain region is connected, then current flow is allowed, but trigger voltage walk-in occurs during multiple ESD events
Solution Approach 1:
The extended drain region is pre-insulated with an insulating film before ESD events occur. This preliminary insulation prevents trigger voltage walk-in during multiple ESD events while still allowing the circuit to function correctly, ensuring consistent protection across repeated events
Solution Approach 2:
An insulating film (thin film structure) is applied to the extended drain region. This thin film provides electrical insulation to prevent charge accumulation and trigger voltage drift, while the underlying structure remains intact to maintain circuit functionality
3Device complexity
If protection circuitry is closely associated with active circuitry, then integration is high, but design flexibility is limited
Solution Approach 1:
The protection circuit is designed as separable functional blocks (SCR, extended drain transistor, insulation structures) that can be independently configured. This segmentation maintains high integration with active circuitry while providing design flexibility to adapt protection parameters to different application requirements
Solution Approach 2:
The patent enables independent adjustment of protection circuit parameters such as trigger voltage, breakdown voltage, and insulation characteristics. These parameter changes allow the protection circuit to be adapted to different voltage levels and ESD protection requirements without redesigning the entire integrated structure
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively diverts excessive voltage from active LDMOS transistors, preventing damage and maintaining consistent ESD protection across multiple events by reducing metal migration and ensuring a uniform trigger voltage.
Implementation Method 1
incorporating a silicon controlled rectifier (SCR) and an extended drain region transistor that diverts charge away from active LDMOS output driver transistors
Implementation Method 2
protection circuits are often connected to I/O bonding pads of an integrated circuit to safely dissipate energy associated with ESD events away from active circuitry
Data Source
AI summary
A circuit with electrostatic discharge protection is described. In one case, the circuit includes trigger device configured to protect a component connected to a node of the circuit during an electrostatic discharge event, the trigger device includes an isolation structure interposed between a gate oxide layer and an extended drain region. A portion of the extended drain region proximate the isolation structure is substantially metal-free.