ESD Protection Circuit Area Reduction via Interconnect Capacitor Stacking
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Solution Overview
Problem
The existing ESD protection circuits in semiconductor integrated circuits face challenges in reducing the area increase due to increased capacitance values, particularly when using RC delays, which leads to larger resistive and capacitive elements, thereby increasing the overall area of the semiconductor integrated circuit device.
Innovation Solution
The semiconductor integrated circuit device incorporates an ESD protection circuit with a resistive element and capacitive element connected in series, featuring a protecting element and a controller that controls the conductive state based on the potential at the connect node between the resistive and capacitive elements, where the capacitive element includes an interconnect capacitor in the interconnect layers that overlaps with the resistive and protecting elements, effectively reducing the area increase by utilizing interconnect layers as capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If RC delay is used in ESD protection circuit, then abnormal current discharge speed is improved, but area of resistive element and capacitive element increases
Solution Approach 1:
The patent transitions the capacitive element from a planar configuration to a three-dimensional stacked configuration by placing capacitor electrodes in different interconnect layers above each other. This vertical stacking approach increases capacitance density without expanding the lateral area of the ESD protection circuit, thereby maintaining fast discharge speed while reducing circuit area.
Solution Approach 2:
The patent reuses existing interconnect layers and wiring structures in the semiconductor device to form capacitor electrodes, rather than dedicating separate structures solely for capacitance. This multi-functional use of interconnect layers reduces the overall area required for the ESD protection circuit while maintaining the necessary RC delay characteristics for abnormal current discharge.
2Reliability
If capacitance value of capacitive element is increased, then ESD protection effectiveness is improved, but area of semiconductor integrated circuit device increases
Solution Approach 1:
The patent achieves increased capacitance value by stacking capacitor electrodes vertically across multiple interconnect layers. This three-dimensional arrangement increases the effective capacitance area without proportionally increasing the lateral footprint, allowing enhanced ESD protection while minimizing area increase in the semiconductor integrated circuit device.
Solution Approach 2:
The patent combines the capacitive element structure with the existing interconnect layers and wiring architecture of the semiconductor device. By merging the capacitor electrodes with conductive interconnect structures that already exist in the device, the patent increases capacitance value without requiring separate dedicated area for the capacitive element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces the area increase caused by increased capacitance values, allowing for a more compact semiconductor integrated circuit design while maintaining effective ESD protection.
Implementation Method 1
at least part of the capacitive element includes an interconnect capacitor provided in the interconnect layers
Data Source
AI summary
An ESD protection circuit includes a resistive element, a capacitive element, a protecting element, and a controller. The resistive element, the protecting element, and the controller are provided in an element formation layer. At least part of the capacitive element includes an interconnect capacitor provided in a plurality of interconnect layers. When viewed in plan, at least part of a capacitance formation region in which the interconnect capacitor is provided overlaps at least part of an element formation region in which the resistive element, the protecting element, and the controller are provided.