Power Reduction In Field Effect Transistors TRIZ Cases
- Z2-FET Inverter Circuit With Segmented Switches
Segmented Z2-FET switches invert signals through potential control, reducing manufacturing precision requirements for doped regions.
- Asymmetric Hysteresis Capacitor for Crowbar Current Reduction
An asymmetric hysteresis capacitor modulates PMOS transistor switching speed to lower dynamic current spikes in CMOS logic circuits.
- FPGA Look-Up Table Single-Direction Pass Gate Architecture
Single-direction pass gate alignment reduces silicon area and power consumption by simplifying routing and improving manufacturing precision.
- Semiconductor Memory Body Bias Control for Leakage and Power-Down Exit
A body bias generator down-converts power supply voltage to provide dynamic body voltages for semiconductor memory transistors.
- Six-Electrode Transistor Leakage Insensitive Circuit
Segmented gates suppress standby power dissipation, enabling lower supply voltage operation without process changes.
- PMOS MRAM Cell Using Negative Voltage to Reduce Switch Resistance
Applying negative voltage to a PMOS switch eliminates body effect and source degeneration, reducing resistance to improve MRAM storage density.
- SOI Transistor Reverse Body Bias Power Island Isolation
Reverse body bias disables SOI output terminals, eliminating isolation cells and reducing leakage current in power islands.
- Semiconductor Device Using Four-Transistor Unit Cell for Low Voltage Data Retention
A semiconductor device uses a four-transistor unit cell to switch between conducting and non-conducting states via node potential control.
- Semiconductor Device Back Gate Potential Control
A semiconductor device maintains a constant back gate potential using an internal voltage generation circuit and battery.
- Semiconductor Logic Element Segmentation for Low Power
A semiconductor logic element uses segmented field effect transistors to isolate internal nodes and control charge flow.
- Power Gating Headswitch Leakage Reduction via Dynamic Control Voltage
A voltage generator adjusts the control voltage of a power gating headswitch to maintain a super-cut off state.
- Power Gating Circuit Voltage Monitoring Data Retention
A power gating circuit monitors voltage levels to control switch states for logic blocks.
- High Speed Buffer Circuit Dynamic Body Biasing
Dynamic body biasing in a high speed buffer circuit minimizes crowbar current during switching transitions.
- Oxide Semiconductor Signal Processing Unit for Low Power Data Retention
A signal processing unit uses oxide semiconductor transistors to hold data in storage circuits without power.
- Dynamic Body Bias Generator for Ultra-Low Voltage CMOS
A body bias generator circuit switches between supply voltages to modulate transistor thresholds in digital logic.
- ESD Protection Circuit Area Reduction via Interconnect Capacitor Stacking
An ESD protection circuit utilizes interconnect capacitors stacked across multiple metal layers to increase capacitance density.
- CMOS Inverter Leakage Suppression via Gate Capacitance Delay
Gate capacitances delay PMOS and NMOS switching to reduce through current without adding external components.