PMOS MRAM Cell Using Negative Voltage to Reduce Switch Resistance

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Solution Overview

Problem

Conventional magnetoresistive random access memory (MRAM) cells face challenges in increasing storage density and reducing fabrication costs due to high resistance in switch transistors caused by body effects and source degeneration, making it difficult to switch between storage states effectively.

Innovation Solution

The use of a PMOS transistor with a negative control voltage and a smaller-size switch transistor reduces the resistance and allows successful switching between storage states, enabling efficient operation and reducing the size of the MRAM cell array.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a NMOS transistor is used as the switch transistor in conventional MRAM cells, then the device can operate with positive voltages, but the body effect and source degeneration cause high resistance that prevents effective switching between storage states

Engineering Contradiction:

Improveswitching effectivenessVSAvoidbody effect and source degeneration

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent inverts the conventional approach by using a PMOS transistor instead of NMOS and applying negative voltages instead of positive voltages. This inversion eliminates the body effect and source degeneration problems that plague NMOS-based MRAM cells, enabling effective switching between storage states while maintaining low resistance in the switch transistor.

Inventive Principle:

Principle #13The other way round (Inversion)

Solution Approach 2:

The patent changes the voltage parameter from positive to negative, and changes the transistor type from NMOS to PMOS. These parameter changes fundamentally alter the electrical characteristics of the switch transistor, eliminating the harmful body effect and source degeneration while enabling reliable switching operation.

Inventive Principle:

Principle #35Parameter changes

2Area of stationary object

If the size of the switch transistor is reduced to increase storage density, then more cells can be packed into the same area, but the resistance increases and switching becomes ineffective

Engineering Contradiction:

Improvestorage densityVSAvoidhigh resistance

Core Design Contradiction:

Area of stationary objectVSObject-affected harmful factors

Solution Approach 1:

By inverting to PMOS technology and using negative voltages, the patent achieves low resistance even in miniaturized transistors. The PMOS transistor structure with negative voltage biasing eliminates the body effect and source degeneration that cause resistance to increase in scaled-down NMOS devices, enabling both high density and effective switching.

Inventive Principle:

Principle #13The other way round (Inversion)

3Reliability

If larger switch transistors are used to reduce resistance, then switching between storage states becomes effective, but the device area increases and storage density decreases

Engineering Contradiction:

Improveswitching effectivenessVSAvoiddevice area

Core Design Contradiction:

ReliabilityVSArea of stationary object

Solution Approach 1:

The patent changes the fundamental electrical parameters by using PMOS transistors with negative voltage operation. This parameter change allows the use of smaller transistor sizes while maintaining low resistance and effective switching, thereby reducing device area and increasing storage density without sacrificing switching reliability.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively increases storage density and reduces fabrication costs by minimizing the size of the switch transistor and maintaining low resistance, allowing successful switching between storage states in MRAM cells.

Implementation Method 1

the storage element 120 is a magnetic tunnel junction (MTJ)... in case that the magnetization directions of the pin layer 122 and the free layer 126 are different, the storage element 120 has the higher impedance... in case that the magnetization directions of the pin layer 122 and the free layer 126 are identical the storage element 120 has the lower impedance

Methodology Applied

Scientific EffectMagnetoresistance: Magnetoresistance

Implementation Method 2

The switch transistor Ms is a PMOS transistor... a control voltage Vctrl with a negative voltage level is provided to the control terminal... the magnitude of the second voltage is higher than a magnitude of the control voltage

Methodology Applied

Scientific EffectField effect: Electric Field

Data Source

PatentUS11108395B2Memory cell and memory cell array of magnetoresistive random access memory operated by negative voltage

Publication Date: 2021.08.31 EMEMORY TECH INC

AI summary

A memory cell of MRAM includes a PMOS transistor and a storage element. A first terminal of the PMOS transistor is connected with a first end of the memory cell. A control terminal of the PMOS transistor is connected with a second end of the memory cell. A first terminal of the storage element is connected with a second terminal of the PMOS transistor. A second terminal of the storage element is connected with a third end of the memory cell. During a write operation, a first voltage is provided to the first end of the memory cell, a second voltage is provided to the third end of the memory cell, and a control voltage is provided to the second end of the memory cell. Consequently, the memory cell is in a first storage state.