High Speed Buffer Circuit Dynamic Body Biasing

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Solution Overview

Problem

In advanced semiconductor processing nodes, such as 28 nm feature size and smaller, leakage current between the source and drain terminals of transistors and crowbar current during signal transitions are significant issues in large integrated circuits, necessitating reduced leakage current, especially in open circuit conditions.

Innovation Solution

The implementation of a high-speed inverter circuit where the gate and body terminals of transistors are connected, allowing well biasing to track the gate voltage, dynamically controlling crowbar current and total leakage, thereby reducing switching energy and overall leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If transistors are operated at advanced processing nodes (28 nm and smaller) to achieve faster operation, then switching speed is improved, but leakage current and crowbar current increase significantly

Engineering Contradiction:
Improveswitching speedVSAvoidleakage current
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The patent applies dynamic body biasing by connecting the body terminal to the gate terminal through a capacitor, allowing the body potential to dynamically track the gate voltage during switching transitions. This dynamic adjustment reduces crowbar current during transitions while maintaining fast switching speeds, resolving the contradiction between speed and energy loss.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the body bias parameter dynamically by coupling it to the gate voltage through a capacitor. This parameter change allows the transistor to operate with optimized body potential during different phases of switching, reducing leakage current while maintaining high-speed performance at advanced 28 nm processing nodes.

Inventive Principle:
Principle #35Parameter changes

2Speed

If transistors are operated at advanced processing nodes (28 nm and smaller) to achieve faster operation, then switching speed is improved, but crowbar current during signal transitions increases

Engineering Contradiction:
Improveswitching speedVSAvoidcrowbar current
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The patent applies dynamic body biasing by connecting the body terminal to the gate terminal through a capacitor, allowing the body potential to dynamically track the gate voltage during switching transitions. This dynamic adjustment reduces crowbar current during transitions while maintaining fast switching speeds, resolving the contradiction between speed and harmful factors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent converts the potentially harmful body effect into a beneficial mechanism by using the gate voltage itself to control the body potential. The capacitor-coupled body terminal uses the gate voltage waveform to dynamically adjust body bias, transforming what would normally be a source of crowbar current into a mechanism that suppresses it.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

3Loss of energy

If gate and body terminals are connected to dynamically control well biasing, then leakage current is reduced, but circuit complexity increases

Engineering Contradiction:
Improveleakage currentVSAvoidcircuit complexity
Core Design Contradiction:
Loss of energyVSDevice complexity

Solution Approach 1:

The patent implements self-service by having the transistor's own gate voltage control its body potential through the capacitor coupling. The gate voltage waveform directly drives the body terminal, eliminating the need for external biasing circuits or control logic, thus reducing leakage current without significantly increasing circuit complexity.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11616506B2High speed buffer circuit
Publication Date: 2023.03.28 NXP USA INC
  • US11616506B2 patent drawing
  • US11616506B2 patent drawing

AI summary

A circuit includes a P-channel transistor formed in a P-well and an N-channel transistor formed in an N-well. The first P-channel transistor has a control electrode connected to the P-well. The N-channel transistor is coupled in series with the P-channel transistor and has a control electrode connected to the N-well. Connecting the control electrodes of the P-channel and N-channel transistors to respective P-well and N-well effectively reduces crowbar current in the circuit.