Six-Electrode Transistor Leakage Insensitive Circuit
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Solution Overview
Problem
Traditional CMOS transistor designs face significant challenges with leakage current as they are scaled down, leading to appreciable power dissipation issues, particularly through source-to-drain leakage currents, which hinder the reduction of supply voltage and subsequent device power consumption.
Innovation Solution
The introduction of six-electrode transistors with four control electrodes (two gate electrodes and two body electrodes) effectively terminates the conductive path for leakage current, reducing or eliminating short-circuit and standby power dissipation by orders of magnitude, allowing for a lower threshold voltage and reduced switching energy without altering materials or process technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS transistors are scaled smaller according to Moore's law, then device density and integration are improved, but power dissipation through leakage currents increases exponentially
Solution Approach 1:
The transistor gate is segmented into two separate gates (first gate and second gate) that can be independently controlled. This segmentation allows one gate to control the primary current flow while the other gate controls the body potential, enabling independent optimization of drive current and leakage current suppression without requiring further scaling.
Solution Approach 2:
The invention changes the electrical parameters by applying different voltages to the two gates. The first gate voltage controls the threshold voltage for normal operation, while the second gate voltage controls the body potential to suppress leakage currents. This parameter control mechanism allows the transistor to maintain low leakage without requiring smaller dimensions.
2Loss of energy
If supply voltage is reduced to lower device power consumption, then energy efficiency is improved, but leakage currents become more significant and harder to control
Solution Approach 1:
By applying specific voltage combinations to the two gates, the transistor can operate at lower supply voltages while maintaining effective leakage control. The first gate controls the channel formation and the second gate controls the body potential, allowing the device to achieve low-power operation with suppressed leakage currents even at reduced voltage levels.
Solution Approach 2:
The second gate acts as an intermediary control element that specifically targets the body potential to suppress leakage currents. This intermediary control mechanism allows independent management of leakage without affecting the primary switching function controlled by the first gate, enabling effective leakage control at lower operating voltages.
3Device complexity
If traditional three- or four-electrode CMOS transistor designs are used, then device simplicity and ease of manufacture are maintained, but leakage current paths cannot be effectively terminated
Solution Approach 1:
The gate control function is segmented into two separate gates, where the first gate controls the channel and the second gate controls the body potential. This segmentation provides an additional control dimension that enables effective termination of leakage current paths without significantly increasing manufacturing complexity, as both gates can be formed using standard CMOS fabrication processes.
Solution Approach 2:
The six-electrode transistor structure maintains compatibility with standard CMOS fabrication processes while providing enhanced functionality. The additional two electrodes (second gate and body) are integrated into the existing manufacturing flow, allowing the device to provide both normal switching function and leakage suppression using the same fabrication infrastructure.
Data Source
AI summary
A leakage insensitive transistor includes a substrate, a source region, a drain region, a channel region between the source region and drain region, a gate dielectric on the channel region, first and second electrodes on the gate dielectric, and third and fourth electrodes on the substrate. The leakage insensitive transistor may be operated by applying a first logic signal to the first electrode, floating the second electrode of the FET, applying a second logic signal opposite the first logic signal to the third electrode, and floating the fourth electrode. A logic circuit may include multiple leakage insensitive transistors.