Semiconductor Device Using Four-Transistor Unit Cell for Low Voltage Data Retention
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Solution Overview
Problem
Current programmable logic devices face challenges in reducing power consumption and data retention during power interruptions, particularly due to the high voltage requirements for writing data in floating gate transistors, which also lead to gate insulating layer deterioration and low data read/write speed.
Innovation Solution
A semiconductor device with a programmable circuit using a unit cell structure comprising four transistors and an analog element, where the output is controlled by the potentials of two nodes, allowing switching between conducting, non-conducting, and conducting states, and utilizing wide bandgap semiconductors to reduce power consumption and improve data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If floating gate transistors are used to make the memory unit nonvolatile, then data retention during power interruption is improved, but power consumption increases due to high potential requirements for electron injection
Solution Approach 1:
The patent changes the operating voltage parameter from high voltage (required by floating gate transistors) to low voltage (1.8V or lower) by using a different memory mechanism based on transistor threshold voltage adjustment through charge trapping in an insulating layer, eliminating the need for high potential electron injection while maintaining data retention capability
Solution Approach 2:
The patent replaces the floating gate transistor mechanism (which requires high voltage electron injection) with a charge trapping mechanism in an insulating layer above the gate electrode, using low voltage charge accumulation to achieve the same nonvolatile memory function without the harmful high voltage requirements
2Reliability
If floating gate transistors are used for data writing, then nonvolatile memory is achieved, but gate insulating layer deterioration occurs due to tunneling current
Solution Approach 1:
The patent converts the potentially harmful high voltage electron injection process into a beneficial low voltage charge trapping process by using the insulating layer above the gate electrode as a charge storage medium, where charges are trapped through low voltage mechanisms rather than high voltage tunneling, thus protecting the gate insulating layer while achieving nonvolatile memory
Solution Approach 2:
The patent introduces an insulating layer as an intermediary charge storage medium between the gate electrode and the channel, replacing the floating gate structure. This intermediary layer traps charges through low voltage mechanisms, preventing direct high voltage stress on the gate insulating layer while maintaining the nonvolatile memory function
3Reliability
If floating gate transistors are used, then nonvolatile memory is achieved, but data read/write speed decreases
Solution Approach 1:
The patent changes the memory mechanism from floating gate transistor (slow read/write due to high voltage requirements and tunneling processes) to a charge trapping mechanism in an insulating layer that can be charged and discharged rapidly at low voltages, significantly improving data read/write speed while maintaining nonvolatile functionality
Data Source
AI summary
A programmable analog device and an analog device that can retain data even when supply of a power supply potential is interrupted and consumes less power. In a semiconductor device, first to fourth transistors are used as switches in a unit cell including an analog element, and the output of the unit cell switches between a conducting state, a non-conducting state, and a conducting state through the analog element by controlling the potential of a first node where the first transistor and the second transistor are connected and the potential of a second node where the third transistor and the fourth transistor are connected.