DRAM ESD Plug Bi-Layer Segmentation for Aspect Ratio Control
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Solution Overview
Problem
Existing dynamic random access memory (DRAM) electrostatic discharge structures face challenges in reducing the contact area between plugs and substrates without increasing the plug aspect ratio, which can lead to voids and degraded device performance due to high aspect ratios, and require enhanced ESD resistance to prevent damage from electrostatic charges.
Innovation Solution
A method involving a substrate with conductive structures, an interlayer dielectric layer, and a bi-layer plug structure where the sacrificial polysilicon layer forms the lower portion of the plug, allowing for controlled contact area reduction and improved ESD mechanism strength without increasing the plug aspect ratio, and utilizing a patterned photoresist layer to selectively cover the sacrificial polysilicon layer in the ESD region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the contact area between the plug and substrate is reduced to increase electrostatic resistance, then ESD resistance is improved, but the plug aspect ratio increases which can cause voids and degraded device performance
Solution Approach 1:
The plug is segmented into two distinct parts: an upper plug portion made of conductive material and a lower plug portion made of sacrificial polysilicon material. This segmentation allows the upper portion to provide ESD resistance through reduced contact area while the lower portion maintains structural support, thereby resolving the contradiction between increasing ESD resistance and avoiding high aspect ratio problems.
Solution Approach 2:
Different materials are used for different portions of the plug to achieve different local functions. The upper portion uses conductive material for ESD protection, while the lower portion uses sacrificial polysilicon for structural support during manufacturing. This local differentiation allows each portion to optimize its specific function without compromising the other.
2Reliability
If the contact area between the plug and substrate is reduced, then electrostatic resistance is increased, but the mechanism strength of the ESD region is degraded
Solution Approach 1:
The plug structure is divided into upper and lower portions with different materials and functions. The upper conductive portion provides ESD resistance through reduced contact area, while the lower sacrificial polysilicon portion provides mechanical strength and structural support during the manufacturing process, thus resolving the contradiction between increasing electrostatic resistance and maintaining mechanism strength.
Solution Approach 2:
The lower plug portion made of sacrificial polysilicon acts as an intermediary structural element that supports the upper conductive portion during manufacturing. This intermediary structure allows the upper portion to be optimized for ESD resistance without compromising the overall mechanical strength of the ESD region.
3Ease of manufacture
If a conventional single-layer plug structure is used, then the manufacturing process is simpler, but the ESD resistance and structural integrity cannot be simultaneously optimized
Solution Approach 1:
The plug is segmented into upper and lower portions with different materials deposited in sequence. The lower polysilicon layer is deposited first and patterned, then the upper conductive layer is deposited and patterned separately. This segmented approach allows independent optimization of each layer's properties while maintaining a relatively straightforward manufacturing process.
Solution Approach 2:
The lower plug portion made of sacrificial polysilicon is formed in advance before the upper conductive portion is added. This preliminary action establishes the structural foundation and contact area control early in the manufacturing process, enabling subsequent optimization of the upper portion for ESD resistance without compromising structural integrity.
Data Source
AI summary
The invention provides a dynamic random access memory (DRAM) with an electrostatic discharge (ESD) region. The upper portion of the ESD plug is metal, and the lower portion of the ESD plug is polysilicon. This structure may improve the mechanical strength of the ESD region and enhance thermal conductivity from electrostatic discharging. In addition, the contact area between the ESD plugs and the substrate can be reduced without increasing aspect ratio of the ESD plugs. The described structure is completed by a low critical dimension controlled patterned photoresist, such that the processes and equipments are substantially maintained without changing by a wide margin.