Integrated Diode Resistor ESD Protection Circuit

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Solution Overview

Problem

Conventional ESD protection circuits require significant semiconductor area due to the need for multiple components like diodes and transistors, and are complex and costly to implement, especially for bidirectional protection where voltage can swing to both positive and negative, necessitating full electrical isolation.

Innovation Solution

A semiconductor device with a diode and resistor integrated into a substrate, where the resistor's value varies with voltage, providing a single-diode bidirectional ESD protection circuit that reduces component count and area usage, and includes an ESD clamp for additional protection, allowing for adjustable layout parameters to suit specific applications.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional ESD protection circuits are implemented with multiple components (diodes, transistors), then reliable ESD protection is achieved, but significant semiconductor area is consumed

Engineering Contradiction:
ImproveESD protection reliabilityVSAvoidsemiconductor area
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent combines multiple ESD protection functions into a single integrated structure using one diode and one resistor formed in the substrate. The diode anode connects to the protected node, the diode cathode connects to a first voltage potential, and the resistor connects between the diode anode and a second voltage potential, creating a compact bidirectional protection circuit that eliminates the need for separate components while maintaining protection reliability

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The single diode-resistor configuration provides universal bidirectional ESD protection for nodes with voltage swinging between positive and negative potentials. The circuit simultaneously handles positive ESD events (when the protected node exceeds the first voltage potential) and negative ESD events (when the protected node falls below the second voltage potential), making it applicable to a wide range of voltage conditions without requiring circuit modification

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If full electrical isolation is implemented for bidirectional protection, then protection effectiveness is improved, but device complexity and cost increase

Engineering Contradiction:
Improvebidirectional protection effectivenessVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The resistor's resistance value automatically adjusts based on the voltage conditions at its terminals. During normal operation with voltage swinging between positive and negative potentials, the resistor maintains a high resistance state that provides electrical isolation. During ESD events, the resistor dynamically changes its resistance to provide appropriate current paths, eliminating the need for external control circuits or switches

Inventive Principle:
Principle #25Self-service

3Ease of manufacture

If fixed resistance values are used in ESD protection circuits, then circuit design is simplified, but adaptability to varying voltage conditions is reduced

Engineering Contradiction:
Improvecircuit design simplicityVSAvoidvoltage condition adaptability
Core Design Contradiction:
Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The resistor is configured to have its resistance value dynamically determined by the voltage conditions at its terminals rather than being a fixed value. The resistance varies based on the potential difference between the diode anode and the second voltage potential, allowing the circuit to automatically adapt to different operating voltages and ESD event magnitudes without requiring manual adjustment or selection of different resistance values

Inventive Principle:
Principle #15Dynamics

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution reduces the semiconductor area required for ESD protection, simplifies the circuit design, and provides effective bidirectional protection with adjustable resistance to accommodate varying voltage conditions, minimizing interference with normal circuit operations while ensuring robust ESD event handling.

Implementation Method 1

At least one opening in the isolation tank forms a resistive path for current to flow between the substrate and the third doped semiconductive region

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Implementation Method 2

The second doped semiconductive region and the third doped semiconductive region form a diode

Methodology Applied
Scientific EffectDiode effect: Diode

Data Source

PatentUS10861843B2Electrostatic discharge protection device
Publication Date: 2020.12.08 TEXAS INSTRUMENTS INC
  • US10861843B2 patent drawing
  • US10861843B2 patent drawing
  • US10861843B2 patent drawing

AI summary

Semiconductor devices including a diode and a resistor are disclosed herein. An example of a semiconductor device includes a substrate having a surface. A first doped semiconductive region is disposed in the substrate below the surface. A second doped semiconductive region is disposed in the substrate and extends between the surface and the first doped semiconductive region. The second doped semiconductive region is at least partially in contact with the first doped semiconductive region. The first doped semiconductive region and the second doped semiconductive region together define an isolation tank. A third doped semiconductive region is disposed in the isolation tank and is in contact with the surface. The second doped semiconductive region and the third doped semiconductive region form a diode. At least one opening in the isolation tank forms a resistive path for current to flow between the substrate and the third doped semiconductive region.