Semiconductor Power Device ESD Protection Diode Dopant Diffusion Control

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Solution Overview

Problem

Existing semiconductor power devices, such as trench MOSFETs integrated with ESD protection diodes, face challenges with high Igss and BVgss standard deviation due to dopant out-diffusion issues during source activation, leading to unstable yield and low ESD capability.

Innovation Solution

A dopant out-diffusion suppression layer is formed after source dopant implantation, acting as a first contact interlayer to prevent non-uniform dopant diffusion, significantly reducing Igss and BVgss standard deviation by depositing an un-doped oxide layer and potentially incorporating additional Fluorine implantation for further suppression.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If source dopant ion implantation is performed without dopant out-diffusion suppression layer, then manufacturing process is simpler, but Igss and BVgss standard deviation increases due to non-uniform dopant diffusion

Engineering Contradiction:

Improvemanufacturing process simplicityVSAvoidIgss and BVgss standard deviation

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

A dopant out-diffusion suppression layer (oxide layer) is deposited on the poly-silicon layer surface before source dopant ion implantation. This preliminary action prevents dopant out-diffusion during subsequent thermal processing, ensuring uniform dopant distribution and reducing Igss and BVgss standard deviation while maintaining manufacturing feasibility

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The oxide layer acts as an intermediary barrier between the source dopant and the poly-silicon layer. It allows controlled dopant diffusion into the poly-silicon while preventing unwanted out-diffusion, thereby achieving uniform doping profiles and consistent electrical characteristics without significantly complicating the manufacturing process

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If Igss is kept high to achieve lower BVgss and improve ESD capability, then ESD protection is enhanced, but Igss exceeds specification limit of 10 uA

Engineering Contradiction:

ImproveESD capabilityVSAvoidIgss specification compliance

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The oxide suppression layer controls the 'flow' of dopant atoms during thermal diffusion, preventing excessive dopant out-diffusion. This control enables achieving the desired dopant concentration profile that produces lower BVgss (improved ESD capability) while keeping Igss within specification limits

Inventive Principle:

Principle #29Pneumatics and hydraulics

Solution Approach 2:

By introducing the oxide suppression layer, the dopant diffusion parameters are changed - the diffusion rate and distribution are controlled, enabling simultaneous achievement of low BVgss (for ESD protection) and controlled Igss (within 10 uA spec) through modified diffusion kinetics

Inventive Principle:

Principle #35Parameter changes

3Reliability

If dopant out-diffusion suppression layer is added to reduce Igss and BVgss standard deviation, then yield stability is enhanced, but device complexity increases

Engineering Contradiction:

Improveyield stabilityVSAvoidlayer structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The oxide suppression layer is deposited as a preliminary step before dopant implantation and thermal processing. This single additional layer prevents dopant out-diffusion issues, significantly improving yield stability and electrical characteristic consistency without requiring complex multi-layer structures or additional processing steps

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The oxide suppression layer is applied locally on the poly-silicon layer surface where dopant implantation occurs. This localized approach provides precise control over dopant diffusion at the critical interface, improving yield stability without adding unnecessary complexity to the overall device structure

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution enhances yield stability by maintaining Igss within specifications while lowering BVgss, thereby improving ESD capability and reducing power consumption.

Implementation Method 1

a dopant out-diffusion suppression layer is formed after source dopant implantation, acting as a first contact interlayer to prevent non-uniform dopant diffusion

Methodology Applied

Scientific EffectDopant out-diffusion suppression: Diffusion Barrier

Implementation Method 2

significantly reducing Igss and BVgss standard deviation by depositing an un-doped oxide layer

Methodology Applied

Scientific EffectPhysical vapor deposition: Physical Vapour Deposition

Implementation Method 3

potentially incorporating additional Fluorine implantation for further suppression

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS8658492B2Semiconductor power device integrated with ESD protection diodes

Publication Date: 2014.02.25 FORCE MOS TECH CO LTD

AI summary

A semiconductor power device integrated with ESD protection diode is disclosed by offering a dopant out-diffusion suppression layers prior to source dopant activation or diffusion to enhance ESD protection capability between gate and source.