ESD Protection Structure Using Isolation Trench and Epitaxial Layer
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Solution Overview
Problem
Conventional ESD protection structures in IC devices using SOI technology face limitations in miniaturization due to large footprints and poor robustness against ESD gun stress tests, particularly failing to meet automotive standards and experiencing current focalization issues.
Innovation Solution
An ESD protection structure is formed within an isolation trench in a semiconductor substrate, where the peripheral region of the epitaxial layer is not enclosed by a deep well structure, reducing the width of the ESD protection structure and creating a uniform PN junction to prevent parasitic MOS formation and current focalization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection structures are implemented with SOI technology, then ESD protection is provided, but the footprint is large which limits miniaturization
Solution Approach 1:
The patent removes the deep well structure from the peripheral region of the ESD protection structure, extracting only the necessary components (isolation trench and epitaxial layer) while eliminating unnecessary elements. This extraction reduces the footprint while maintaining ESD protection functionality in the core region.
Solution Approach 2:
The patent applies different structural qualities to different regions: the peripheral region uses a simplified structure (isolation trench + epitaxial layer) while the core region maintains the full thyristor structure with deep well. This local differentiation optimizes the footprint by reducing structure complexity where full protection is not needed.
2Reliability
If conventional ESD protection structures are implemented with SOI technology, then ESD protection is provided, but current focalization causes hotspots reducing robustness
Solution Approach 1:
The deep well structure that causes current focalization and hotspots is extracted/removed from the peripheral region. This eliminates the source of current concentration while preserving the essential ESD protection function through the isolation trench and epitaxial layer configuration.
3Reliability
If deep well structure is used to enclose peripheral region, then ESD protection is enhanced, but device width increases
Solution Approach 1:
The deep well structure is extracted from the peripheral region, removing the source of width increase. The patent demonstrates that ESD protection can be achieved without this enclosing structure by using the isolation trench and epitaxial layer configuration alone.
Solution Approach 2:
Different structural approaches are applied to different regions: the peripheral region uses a compact structure without deep well enclosure, while the core region uses the full thyristor structure. This local quality differentiation reduces overall device width while maintaining necessary protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the minimum size of IC devices that can be achieved while enhancing the robustness against ESD gun stress tests by minimizing parasitic MOS structures and current focalization, improving the overall performance of ESD protection.
Implementation Method 1
creating a uniform PN junction to prevent parasitic MOS formation and current focalization
Implementation Method 2
ESD currents are to be shunted
Data Source
AI summary
An ESD protection structure formed within an isolation trench and comprising a first peripheral semiconductor region of a first doping type, a second semiconductor region of the first doping type, and a semiconductor structure of a second doping type opposite to the first doping type formed to provide lateral isolation between the semiconductor regions of the first doping type and isolation between the further semiconductor region of the first doping type and the isolation trench. The semiconductor structure of the second doping type is formed such that no semiconductor region of the second doping type is formed between a peripheral side of the first semiconductor region of the first doping type and a wall of the isolation trench, and no semiconductor region of the first doping type is in contact with the isolation trench other than the first semiconductor region of the first doping type.