ESD Protection Device With Segmented N-Well Diodes
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Solution Overview
Problem
Conventional ESD protection devices, such as zener diodes, have trigger and holding voltages that are too high, leading to potential damage to semiconductor junctions and gate structures in VLSI circuits during electrostatic discharge events, especially with the advancement of semiconductor technology where sub-80 nm gate dielectrics have breakdown voltages close to or less than 3-4 V.
Innovation Solution
The design incorporates a P-type substrate set as floating, with multiple N-wells and P-doped regions forming diodes and parasitic BJTs, which are electrically connected to create additional current paths with lower impedance, allowing for effective discharge of electrostatic charges at lower voltages, thus reducing the holding voltage and improving reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional zener diode is used for ESD protection, then the device structure is simple, but the trigger voltage and holding voltage are too high to protect sub-80 nm gate dielectrics
Solution Approach 1:
The ESD protection device is segmented into multiple functional regions: a first region with a first conductivity type substrate and first semiconductor layer, a second region with a second conductivity type substrate and second semiconductor layer, and a third region coupling them. This segmentation allows each region to be optimized independently, achieving low trigger voltage and holding voltage while maintaining structural organization.
Solution Approach 2:
The patent merges two different conductivity type structures (first and second regions) into a single ESD protection device, combining their protective functions. The coupling region integrates the transition between different conductivity types, creating a unified structure that leverages the advantages of both regions to achieve superior ESD protection with reduced voltages.
2Reliability
If the trigger voltage is reduced to protect gate dielectrics, then the protection capability improves, but the holding voltage may also increase
Solution Approach 1:
Different regions of the device are designed with different local qualities: the first region is optimized for low trigger voltage to protect gate dielectrics, while the second region provides complementary characteristics. The coupling region is specifically designed to manage the transition and control the holding voltage, ensuring that local optimizations contribute to overall performance without compromising other parameters.
Solution Approach 2:
The patent utilizes parameter changes by varying the conductivity types, doping concentrations, and geometric dimensions across different regions. By carefully controlling these parameters in each region and their interfaces, the device achieves both low trigger voltage for gate dielectric protection and controlled holding voltage through precise parameter optimization in the coupling region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the holding voltage and impedance of the ESD protection device, enhancing its ability to handle high discharging currents while preventing damage from electrostatic discharges and avoiding the Darling effect, thereby improving the efficiency and reliability of ESD protection in VLSI circuits.
Implementation Method 1
Each of the P-type doped regions is electrically connected to one of a plurality of I/O terminals, and the N-type doped region is electrically connected to the first common P-doped region and a bus
Implementation Method 2
a first common P-doped region formed in the first common N-well; a second common P-doped region formed on the second common N-well; a third common P-doped region formed between the first common N-well and the second common N-well on the P-type substrate, and the third common N-doped region being electrically connected to the first common N-doped region and the second common P-doped region
Data Source
AI summary
An electrostatic discharge protection device having a P-type substrate, a common N-well formed in the P-type substrate, a common N-doped region formed in the first common N-well, wherein the common N-doped region is electrically connected to a reference voltage node. The device further has a common P-doped region formed in the common N-well, wherein the common P-doped region surrounds the common N-doped region, the common P-doped region and the common N-well form a common diode, a plurality of peripheral N-wells formed in the P-type substrate and surrounding the common N-well, each of the peripheral N-wells comprising a P-type doped region and a N-type doped region, wherein the P-type doped region is electrically connected to one of a plurality of I/O terminals, and a circular P-doped region formed in the P-type substrate and disposed between the common N-well and the peripheral N-wells, and the circular P-doped region surrounding the common N-well.