ESD Protection Semiconductor Device Without STI
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Solution Overview
Problem
Conventional semiconductor devices with shallow trench insulators (STIs) between P and N doped regions result in longer current paths, leading to extended charge/discharge times and reduced discharge speed, making them less effective as ESD devices.
Innovation Solution
The semiconductor device eliminates the STI between P and N doped regions, using conductive materials and specific doped region configurations to create a shorter current path, assisted by conductive layers and voltage configurations to enhance current transmission and discharging speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If STI is provided between P doped region and N doped region to separate the regions, then isolation between P and N doped regions is improved, but current path length is extended and discharge speed is reduced
Solution Approach 1:
The invention removes the STI structure from between the P and N doped regions, extracting the insulating element that was causing the long current path. This allows direct contact between the doped regions, creating a short current path for fast ESD discharge while maintaining isolation through alternative means (p-type isolation layer and n-type isolation layer formed in trenches).
Solution Approach 2:
The invention introduces intermediary isolation structures (p-type isolation layer and n-type isolation layer formed in trenches) that provide electrical isolation between P and N doped regions without extending the current path. These intermediary layers are positioned laterally rather than vertically between the doped regions, allowing direct vertical contact for fast discharge.
2Stability of the object's composition
If STI is provided between P doped region and N doped region, then region separation is achieved, but charge/discharge time is extended
Solution Approach 1:
The STI structure is removed from the vertical path between P and N doped regions, eliminating the time delay caused by current having to bypass the insulating material. Region separation is maintained through lateral isolation layers that do not impede the vertical current flow.
Solution Approach 2:
The isolation function is moved from the vertical dimension (where it previously blocked current) to the lateral dimension (where it provides isolation without affecting vertical current flow). The p-type and n-type isolation layers are positioned sideways between the doped regions, allowing fast vertical discharge while maintaining horizontal separation.
3Stability of the object's composition
If STI is used for isolating P and N doped regions, then isolation is provided, but discharge speed becomes slow making the device less effective as ESD device
Solution Approach 1:
The STI structure is extracted from the current path, eliminating the bottleneck that reduced discharge speed and ESD effectiveness. The isolation function is transferred to lateral structures that do not impede the rapid discharge required for ESD protection.
Solution Approach 2:
The invention changes the configuration of isolation structures from vertical (STI between doped regions) to lateral (isolation layers positioned sideways). This parameter change in the spatial arrangement allows the isolation function to be maintained while the discharge speed parameter is dramatically improved, restoring ESD protection effectiveness.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces discharging time and enhances the protection capabilities of the semiconductor device when used as an ESD device by providing a faster discharge path and improved circuit protection.
Implementation Method 1
a P type substrate (310), an N type substrate (320)... a first doped region of type two (321), provided in the well of type one (311)... a well of type two (322)... and a first doped region of type one (312), doped in the well of type two (322)
Data Source
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AI summary
A semiconductor device comprising a substrate is disclosed. The substrate comprises: a well of type one; a first doped region of type two, provided in the well of type one; a well of type two, adjacent to the well of type one; and a first doped region of type one, doped in the well of type two. The substrate comprises no isolating material provided in a current path formed by the first doped region of type two, the well of type one, the well of type two and the first doped region of type one.