ESD Protection Circuit Using Substrate Capacitor
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing ESD protection circuits for semiconductor devices, particularly in high-capacity and integrated devices, face challenges in effectively managing electrostatic discharge due to insufficient reduction of RC product, especially in Charged Device Model (CDM) scenarios, where the resistive element alone is insufficient to improve ESD tolerance.
Innovation Solution
The proposed ESD protection circuit incorporates a capacitor structure using a semiconductor substrate with a conductive well, dielectric layer, and multilayer interconnects to increase capacitance between nodes, reducing the voltage stress on transistors and enhancing ESD tolerance without increasing chip size, by employing a MOS capacitor configuration and strategically placing contact plugs and interlayer insulating films.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large resistive element is used to provide ESD protection, then ESD protection capability is improved, but chip surface area is increased
Solution Approach 1:
The patent changes the electrical parameters by introducing a capacitive element in parallel with the resistive element. This creates an RC circuit where the capacitor stores electrostatic charge, reducing the burden on the resistor and allowing smaller resistance values to be used effectively, thereby improving ESD protection without proportionally increasing chip area.
Solution Approach 2:
The patent employs a composite protection structure combining resistive and capacitive elements. The resistive element (formed by electrode interconnect) and capacitive element (formed by the capacitor structure with conductive plates and dielectric layer) work together as a composite system to provide enhanced ESD protection while optimizing chip area utilization.
2Loss of energy
If a large resistive element is used to reduce electrostatic charge, then voltage drop is increased, but ESD tolerance is insufficient due to high RC product
Solution Approach 1:
The capacitor acts as an intermediary element that temporarily stores electrostatic charge. During ESD events, the capacitor absorbs the initial charge surge, preventing it from immediately passing through the resistive element. This mediation reduces the RC time constant effect and improves ESD tolerance while maintaining appropriate voltage drop characteristics.
Solution Approach 2:
The capacitor provides beforehand cushioning by pre-charging or being ready to absorb electrostatic discharge before the actual ESD event occurs. This cushioning effect reduces the impact of ESD on the circuit by absorbing the shock, thereby improving ESD tolerance without requiring excessive resistance that would cause problematic voltage drops.
3Reliability
If capacitance is increased to reduce RC product, then ESD tolerance is improved, but device complexity is increased
Solution Approach 1:
The capacitor structure serves multiple functions: it provides the capacitive element for reducing RC product, acts as part of the overall ESD protection circuit, and can be integrated with existing chip interconnect structures. This multi-functionality approach improves ESD tolerance without proportionally increasing device complexity, as the same structural elements serve multiple purposes.
Solution Approach 2:
The patent merges the capacitor structure with the existing electrode interconnect and bonding pad structures. The conductive plates of the capacitor are formed using the same interconnect layers and materials already present in the chip, and the dielectric layer is integrated with the existing insulating structures. This merging approach minimizes additional complexity while achieving the required capacitance for improved ESD tolerance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces the voltage stress on transistors, enhancing ESD protection tolerance by increasing capacitance, thereby preventing device destruction during electrostatic discharge, while maintaining a compact chip design.
Implementation Method 1
the first well of the semiconductor substrate, the dielectric layer, the bonding pad and the interconnect layer constitute a capacitor
Data Source
AI summary
An ESD protection circuit for a semiconductor device including a bonding pad receiving a first power supply voltage; an interconnect layer provided in an underside of the bonding pad so as to be electrically conductive with the bonding pad; a semiconductor substrate provided with a first well of a predetermined conductive type in a predetermined region of a surface layer of the substrate, which first well receives a second power supply voltage having a different voltage from the first power supply voltage and provided with a confronting region confronting the underside of the interconnect layer over a dielectric layer, and the first well of the semiconductor substrate, the dielectric layer, the bonding pad and the interconnect layer constitute a capacitor.