ESD Protection Device With Surface Bypass Path
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Solution Overview
Problem
Existing ESD protection devices for CMOS integrated circuits face challenges in achieving high turn-on speed without increasing capacitive load and protecting monitoring devices from ESD current, which often results in damage.
Innovation Solution
The ESD protection device incorporates a unique structure with protection layers and MOS transistor structures that allow ESD current to be bypassed in a surface area, reducing capacitive load and eliminating the need for a power clamp, while also ensuring the monitoring device is not damaged by ESD current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If poly-silicon regions are used to connect biasing nodes to the well for improving turn-on speed, then the turn-on speed is improved, but the capacitive load increases
Solution Approach 1:
The patent extracts and removes the poly-silicon regions from the structure, replacing them with direct well connections. This eliminates the junction capacitance between poly-silicon and doping regions while maintaining the biasing function, thereby reducing capacitive load without sacrificing turn-on speed.
Solution Approach 2:
The patent changes the structural parameters by eliminating intermediate poly-silicon layers and directly connecting biasing nodes to wells. This structural parameter change reduces the junction area and associated capacitance, achieving lower capacitive load while preserving the electrical performance for fast turn-on.
2Reliability
If ESD current is discharged through conventional paths, then ESD protection is provided, but the monitoring device is damaged by ESD current
Solution Approach 1:
The patent segments the ESD current path by introducing a dedicated ESD bypass path that is separate from the monitoring device path. The MOS transistor structure creates distinct current channels: one for monitoring and one for ESD discharge, allowing ESD current to be shunted away from sensitive monitoring components while maintaining protection functionality.
Solution Approach 2:
The patent introduces an intermediary MOS transistor structure that acts as a mediator between the ESD current source and the monitoring device. This intermediary component provides a controlled low-impedance path for ESD current while isolating the monitoring device from direct exposure to harmful ESD current peaks.
3Reliability
If diodes are used for ESD protection, then ESD protection is provided, but a power clamp is needed which increases device complexity
Solution Approach 1:
The patent makes the MOS transistor structure multi-functional by enabling it to perform both ESD protection and power clamp functions simultaneously. The same transistor structure provides over-voltage protection during normal operation and ESD discharge path during ESD events, eliminating the need for separate power clamp components and reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution provides a high turn-on speed and reduced capacitive load, effectively protecting both the CMOS integrated circuits and the monitoring device from ESD damage, with improved reliability and performance.
Implementation Method 1
a protection layer is disposed between the doping region and the well
Implementation Method 2
two MOS transistor structures are formed in the well... allow ESD current to be bypassed in a surface area
Implementation Method 3
ESD protection device for protecting the monitoring device more efficiently... discharge the ESD current
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
An ESD device disposed on a substrate is provided. The ESD device includes a first well, a second well, a first poly-silicon region, a second poly-silicon region and a first protection layer. The first well has a first conductive type and is disposed on the substrate. The second well has a second conductive type, is disposed on the substrate and is adjacent to the first well. The first poly-silicon region is disposed on the first well. The second poly-silicon region is disposed on the second well. The first protection layer covers portions of the first well, the second well, the first poly-silicon region and the second poly-silicon region. There is no doping region in the portions of the first well and the second well which are covered by the first protection layer and between the first poly-silicon region and the second poly-silicon region.