Multi-Fingered ESD Transistor With Floating Wells
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Solution Overview
Problem
In multi-fingered ESD protection circuits, non-uniform triggering of parasitic bipolar transistors due to varying electric potential under gate fingers leads to inadequate discharge of ESD pulses, and conventional solutions increase transistor size to address this issue.
Innovation Solution
The introduction of elongated floating wells between substrate taps and gate fingers, which isolate substrate taps and force current flow perpendicular to gate fingers, enhancing potential differences and triggering uniformity, allowing for reduced tap distance and transistor size while improving ESD protection performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between substrate tap and gate fingers is increased to enhance potential difference, then ESD protection performance is improved, but transistor size increases substantially
Solution Approach 1:
The substrate tap is segmented into multiple distributed taps positioned beneath different gate fingers. This segmentation allows each tap to serve a specific gate finger, reducing the distance between taps and gate fingers while maintaining uniform potential distribution across the structure, thereby improving ESD protection without increasing overall transistor size
Solution Approach 2:
The substrate tap is repositioned from a peripheral location to a position directly beneath the gate fingers (vertical dimension change). This dimensional reconfiguration reduces the horizontal distance between the tap and gate fingers, enhancing potential difference and triggering uniformity without expanding the transistor's planar footprint
2Reliability
If conventional multi-fingered structure is used to increase total gate width, then ESD discharge capability is improved, but non-uniform triggering occurs due to varying potential under different fingers
Solution Approach 1:
Each gate finger is assigned a dedicated substrate tap positioned directly beneath it, creating localized potential distribution. This ensures that each finger experiences uniform potential conditions, enabling simultaneous and uniform triggering across all fingers while maintaining the multi-fingered structure's high ESD discharge capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution achieves more uniform triggering of parasitic bipolar transistors, increasing the ESD pulse discharge capability and reducing transistor size, with improved performance demonstrated by higher triggering voltage, snapback voltage, and increased current handling capacity compared to prior art devices.
Implementation Method 1
N-type tap 292 makes ohmic contact to N-type well 240 through N-type implant region 290
Implementation Method 2
the triggering of the parasitic bipolar transistor depends on forward biasing the P-N junction between the P-type substrate and the N-type source region
Data Source
AI summary
A multi-fingered gate transistor formed in a substrate of one conductivity type overlying a well of a second conductivity type. Ohmic contact to the well is made by an implanted region of the second conductivity type that circumscribes the gate transistor. Ohmic contact to the substrate is made by taps located on sides of the gate structure between the gate structure and the well contact. Floating wells are located on opposite sides of the gate structure between the substrate taps and the ends of the gates to isolate these substrate taps and force current flow in the substrate under the gate transistor to be substantially perpendicular to the direction in which the gate fingers extend. This increases the potential difference between these substrate regions and source regions in the gate transistor, thereby aiding the triggering of the parasitic bipolar transistors under adjacent gate fingers into a high current state.