ESD Trigger Circuit With Timed Gate Release for Floating Recovery
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Solution Overview
Problem
Conventional ESD protection schemes do not allow the ESD protection gate to float after an ESD event, potentially interfering with normal device operation.
Innovation Solution
A trigger circuit comprising an input terminal, an output terminal, diodes, and transistors configured to activate and deactivate the ESD protection switch during an ESD event, ensuring the gate can float back to its normal operational state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional ESD protection schemes are used, then ESD current can be shunted, but the ESD protection gate cannot float after the ESD event, potentially interfering with normal device operation
Solution Approach 1:
The patent applies the dynamics principle by making the ESD protection switch state variable rather than fixed. The switch dynamically transitions between ON and OFF states based on the ESD event detection and timing circuitry. The gate is held in a defined state during ESD protection and then released to float after the event, allowing the system to adapt its protection behavior to operational conditions.
Solution Approach 2:
The patent implements periodic action through the timing circuit that controls the duration of the ESD protection state. The circuit activates protection for a specific period following ESD detection, then automatically releases the gate to float. This time-based control ensures protection is applied only when needed, allowing normal operation to resume after the protected interval.
2Reliability
If active ESD protection is used, then the operation can be simulated with circuit simulation tools, but the gate remains held and cannot float after the ESD event
Solution Approach 1:
The patent applies preliminary action by pre-configuring the timing circuit and control logic that will automatically manage the gate state after ESD detection. The circuit is designed in advance to hold the gate in a protected state for a predetermined duration, then automatically release it to float without requiring additional control signals. This preliminary setup enables both reliable protection and subsequent gate flexibility.
Solution Approach 2:
The patent implements feedback through the timing circuit that monitors the ESD event and automatically adjusts the gate state accordingly. The feedback mechanism detects when the ESD event has concluded and triggers the release of the gate from its held state, allowing it to float. This closed-loop control ensures the gate transitions appropriately based on actual operational conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The trigger circuit effectively manages ESD events by activating the ESD protection switch during ESD occurrences and returning it to a floating state post-event, preventing interference with normal device operation and ensuring safe current shunting.
Implementation Method 1
The first capacitor is arranged to be discharged through the first resistor to the output terminal such that, when the first capacitor is discharged below a first threshold of the first transistor, the control terminal of the first transistor deactivates the conduction path
Implementation Method 2
a first diode function biased from the output terminal to the input terminal; a second diode function biased from the input terminal to the output terminal
Data Source
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AI summary
A trigger circuit for controlling an ESD protection switch, comprising: - an input terminal arranged to be connected with a first conduction terminal of the ESD protection switch; - an output terminal arranged to control a control terminal of the ESD protection switch; - a first diode function biased from the output terminal to the input terminal ; - a second diode function biased from the input terminal to the output terminal and connected in series with the first diode function ; - a first transistor having two conduction terminals and a control terminal; wherein the two conduction terminals of the first transistor are arranged in parallel with the first diode function and wherein the control terminal of the first transistor is configured for controlling a conduction path between the two conduction terminals of the first transistor; - a first timer circuit comprising: - a first resistor connected in series between the control terminal of the first transistor and the output terminal ; - a first capacitor connected in series between the control terminal of the first transistor and the input terminal ; wherein the second diode function is connected in series between the input terminal and one of the two conduction terminals of the first transistor; wherein the control terminal of the first transistor is coupled via the first capacitor to the input terminal, such that a rising voltage at the input terminal due to an ESD event triggers the control terminal of the first transistor to activate the conduction path between the two conduction terminals of the first transistor; and wherein the first capacitor is arranged to be discharged through the first resistor to the output terminal such that, when the first capacitor is discharged below a first threshold of the first transistor, the control terminal of the first transistor deactivates the conduction path between the two conduction terminals of the first transistor.