Etch Stop Layer Pattern for Vertical Memory Plug Depth Uniformity
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Solution Overview
Problem
Conventional non-volatile memory devices with planar transistor structures face limitations in reliability and efficiency, particularly in vertical memory device manufacturing, where maintaining uniformity and reliability of interlayer heights and plug depths is challenging.
Innovation Solution
A non-volatile memory device with a vertical structure is designed, featuring a substrate with impurity regions, channel regions extending vertically, gate electrodes along the channel regions, insulating interlayers, contact plugs, and an etch stop layer pattern that contacts the insulating interlayers, ensuring uniform heights of interlayers and plug depths through specific manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical transistor structure is adopted to improve memory device integrity, then device reliability is improved, but manufacturing complexity increases due to challenges in maintaining uniform interlayer heights and plug depths
Solution Approach 1:
An etch stop layer is formed on the contact plug before subsequent etching processes. This preliminary action ensures that the contact plug maintains a uniform depth by providing a defined stopping point for etching operations, thereby reducing manufacturing complexity while preserving the reliability benefits of the vertical transistor structure.
Solution Approach 2:
The etch stop layer introduces a material with distinct etching properties that changes the etching process parameters. By selecting a material with different etch selectivity than surrounding layers, the process achieves uniform plug depths and interlayer heights automatically, converting a complex manufacturing challenge into a controlled material property application.
2Ease of manufacture
If conventional planar transistor structures are used, then manufacturing process is simpler, but device reliability and efficiency are limited
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure. This dimensional change enables improved device reliability and efficiency by increasing the channel length without proportionally increasing the device footprint, while the etch stop layer ensures the manufacturing process remains controllable despite the increased complexity.
3Manufacturing precision
If etch stop layer pattern is added to maintain uniform interlayer heights and plug depths, then manufacturing precision is improved, but device structure complexity increases
Solution Approach 1:
The etch stop layer acts as an intermediary element between the contact plug and the insulating interlayer. This intermediate layer provides a controlled interface that ensures uniform etching termination and consistent interlayer heights, achieving high manufacturing precision while adding minimal structural complexity since the layer serves multiple functions (etch stop, planarization reference, and potential electrical isolation).
Data Source
AI summary
According to example embodiments of inventive concepts, a non-volatile memory device includes a substrate including a second impurity region crossing a first impurity region, and channel regions extending in a vertical direction on the substrate. Gate electrodes may be separated from each other in a vertical direction and a horizontal direction along outer walls of the channel regions. A first insulating interlayer may be on the gate electrodes and the channel regions, where the first insulating interlayer defines a contact hole between at least one adjacent pair gate electrodes and a contact plug is formed in the contact hole to be electrically connected to the second impurity region. An etch stop layer pattern may be on the contact plug and the first insulating interlayer.