Etch-Stop Layer Control for Multi-Depth Vias and Trenches
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Solution Overview
Problem
Conventional semiconductor manufacturing processes for creating vias and trenches of different depths are time-consuming and complex due to the need for separate processes, which increases costs and complexity, and are affected by the RIE lag phenomenon where depth depends on the width of openings.
Innovation Solution
A method involving the deposition of dielectric layers separated by etch-stop layers, using a non-selective etching process to create openings, and then a selective etching process to reach the etch-stop layers, allowing for the formation of vias and trenches of specific depths regardless of their width, thereby simplifying the process and reducing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate processes are used to create vias and trenches, then manufacturing precision can be maintained, but process complexity and time increase
Solution Approach 1:
The patent combines the creation of vias and trenches into a single integrated process. Multiple openings are created simultaneously in the same dielectric layer using one etching process, eliminating the need for separate via and trench formation processes. This reduces process complexity and time while maintaining depth control through the use of etch-stop layers and selective etching parameters.
Solution Approach 2:
The etching process is designed to serve multiple functions: creating both vias and trenches in different regions of the dielectric layer, achieving different depths for different openings, and forming interconnect structures. This multi-functional approach eliminates the need for separate specialized processes for via and trench formation.
2Manufacturing precision
If separate processes are used for vias and trenches, then depth control is improved, but manufacturing time increases
Solution Approach 1:
The patent merges via and trench formation into a single etching process that operates simultaneously across the entire dielectric layer. Different openings etch to different depths based on their location and the presence of etch-stop layers, achieving precise depth control without requiring separate process steps for each feature type.
Solution Approach 2:
Etch-stop layers are introduced as intermediary structures that control the etching depth for different openings. These layers act as depth markers that stop the etching process at specific locations, allowing simultaneous formation of features at different depths in a single process while maintaining precise depth control.
3Manufacturing precision
If RIE lag phenomenon occurs, then etching depth becomes dependent on opening width, but process simplicity is reduced
Solution Approach 1:
Etch-stop layers serve as intermediary structures that decouple the relationship between opening width and etching depth. By providing physical barriers at specific depths, these layers ensure that etching stops at predetermined locations regardless of the opening width, thereby eliminating the RIE lag effect where deeper openings would otherwise etch further due to their width.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the efficient creation of vias and trenches of precise depths, reducing process complexity and cost by using etch-stop layers to control etching depths, ensuring consistent interconnects across different levels without the need for separate processes for vias and trenches.
Implementation Method 1
The etch-stop layer is configured to prevent the etching process from penetrating deeper than a specific depth
Implementation Method 2
creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process
Data Source
AI summary
Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.