Etching Buffer Layers for Uniform Via Formation in 3D NAND
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Solution Overview
Problem
Existing methods for forming contact structures in three-dimensional high density semiconductor devices face challenges in achieving uniform etching depth and efficient interlayer conductor connection due to non-simple spatial periods and varying etching characteristics of active and insulating layers.
Innovation Solution
A method involving the formation of sub stacks with buffer layers and multiple etching processes to create a stairstep structure of landing areas on active layers, allowing interlayer conductors to extend to these areas, with the buffer layers having different material compositions or thicknesses to accommodate varying etching times and ensure uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form vias through multiple active and insulating layers, then the manufacturing process is simpler, but the etching depth uniformity deteriorates due to non-simple spatial periods and varying etching characteristics of different layers
Solution Approach 1:
The patent divides the etching process into multiple sequential etching steps, where each step targets specific layers (e.g., first etching active layers, then insulating layers, then buffer layers). This segmentation allows each etching step to be optimized for its specific target layers, achieving uniform etching depth despite the non-uniform stack structure with varying spatial periods.
Solution Approach 2:
The patent introduces buffer layers between sub-stacks of active and insulating layers before the etching process. These buffer layers are specifically designed with etching selectivity to protect underlying layers during etching and to define precise etching stop points, ensuring uniform etching depth across layers with different spatial periods.
2Manufacturing precision
If buffer layers with different material compositions or thicknesses are introduced to accommodate varying etching times, then the etching depth uniformity is improved, but the device structure becomes more complex
Solution Approach 1:
The patent introduces buffer layers as intermediary elements between the active/insulating layer stacks and the substrate. These buffer layers serve as etching stop layers and protective layers during the multi-step etching process, enabling precise control of etching depth without requiring complex adjustments to the main active/insulating layer structure.
Solution Approach 2:
The buffer layers are strategically placed only at specific locations where etching depth control is needed, and their material composition and thickness are locally optimized for their specific function as etching stop layers. This localized approach adds minimal complexity only where necessary while maintaining etching uniformity.
3Manufacturing precision
If multiple etching processes are used to form vias through buffer layers and active layers, then the via formation uniformity is improved, but the manufacturing time increases
Solution Approach 1:
The patent segments the via formation process into multiple specialized etching steps, each targeting specific layers with optimized etching parameters. This segmentation improves via formation uniformity by ensuring each layer type is etched under optimal conditions, despite increasing the total process time.
Solution Approach 2:
The patent changes etching parameters (such as etchant composition, temperature, power, and pressure) between different etching steps to optimize each step for its specific target layers. This parameter optimization improves via formation uniformity while minimizing the time required for each individual etching step.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient and uniform formation of vias and interlayer conductors, addressing the challenges of non-simple spatial periods and varying etching characteristics, thereby enhancing the connectivity and density of three-dimensional semiconductor devices.
Implementation Method 1
The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack.
Data Source
AI summary
Vias are formed within a stack of alternating active and insulating layers by forming a first sub stack, a second sub stack over the first sub stack, a first buffer layer therebetween and a second buffer layer under the first sub stack. An upper layer of the first sub stack is exposed through a set of vias by first and second etching processes. The first etching process forms a first set of etch vias through the second sub stack and stops at or in the first buffer layer. The second etching process etches through the first buffer layer to the upper layer of the first sub stack. A third etching process etches through the first set of etch vias, through the first sub stack and stops at or in the second buffer layer. A fourth etching process and etches through the second buffer layer.