Ethernet Switch Timestamp Circuit Reduces Residence Time
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Solution Overview
Problem
The existing IEEE802.1AS protocol, also known as Generalized Precision Time Protocol (gPTP), experiences increased residence time in Ethernet switches due to software processing, which degrades the accuracy of clock synchronization in network communication systems.
Innovation Solution
A device and system architecture that incorporates timestamp circuits at ingress and egress ports to minimize residence time by processing and modifying data frames in hardware, thereby reducing software processing overhead and enhancing timestamp accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If software processing is used to modify data frames in the local CPU, then the gPTP protocol can be implemented flexibly, but the residence time in the Ethernet switch increases significantly
Solution Approach 1:
The patent extracts the time-critical frame modification operations from software processing in the CPU and implements them in hardware circuits within the Ethernet switch. This separation allows software to handle protocol logic while hardware performs rapid timestamping and frame modification, resolving the contradiction between implementation flexibility and processing speed.
Solution Approach 2:
The patent introduces dedicated hardware circuits as intermediaries between the incoming data frames and the CPU. These circuits perform preliminary timestamping and frame modification operations, reducing the burden on software and minimizing the time frames spend in the switch while maintaining protocol flexibility.
2Adaptability or versatility
If software routines are used to measure frequency difference and calculate timestamps, then the system can adapt to different network configurations, but the timestamp accuracy deteriorates due to increased residence time
Solution Approach 1:
The patent replaces software-based timestamping and frequency measurement with dedicated hardware circuits. The hardware timestamp circuits capture precise arrival and departure times, while hardware calculators compute frequency differences and residence times, eliminating software processing delays and significantly improving measurement precision.
Solution Approach 2:
The patent performs timestamping and preliminary calculations in hardware before frames are passed to software processing. By capturing timestamps and computing initial frequency differences in hardware circuits, the system preserves high measurement precision while allowing software to handle adaptive network configuration tasks.
3Adaptability or versatility
If data frames are processed by the local CPU, then the system can handle complex protocol requirements, but the processing speed is much slower than hardware forwarding
Solution Approach 1:
The patent segments the data frame processing into two distinct paths: time-critical operations (timestamping, frequency measurement, residence time calculation) are handled by dedicated hardware circuits, while protocol management and configuration tasks are handled by software in the CPU. This segmentation enables both high-speed processing and complex protocol handling.
Solution Approach 2:
The patent introduces hardware circuits as intermediaries that perform rapid preprocessing of data frames before they reach the CPU. These intermediary circuits handle timestamping and initial calculations at line speed, allowing the CPU to focus on higher-level protocol management without becoming a bottleneck.
Data Source
AI summary
A system for network data transactions, the system including an ingress port to receive data frames and timestamp received data frames, a frame analyzer to forward the data frames to a processor, the processor to extract timing information from the data frames and update the data frames based on updated timing calculations and output updated data frames via one or more egress ports. Data frames are timestamped at ingress and egress ports, and egress timestamps are saved in a timestamp memory. The system reduces overall network delays by using dedicated hardware and stored timestamp information.