Time-Division Multiplex TRIZ Cases
- Deterministic Network Packet Sending Period Determination
Encapsulate timestamp information into packets to help downstream nodes accurately determine sending periods for deterministic network scheduling.
- Precision Time Source Failure Detection in Power Systems
Independent monitoring detects spoofing and jamming attacks on GNSS receivers, ensuring reliable time distribution during primary source failures.
- Multimedia Border Controller for Cross-VPN Security
A multimedia border controller registers endpoints and performs address translation to enable secure communication across virtual private networks.
- IP Fragment Reassembly in Cellular Core Using Encapsulation Headers
An IP packet fragment reassembly system uses encapsulation headers to identify and reassemble fragments before wireless transmission.
- Reversible ADSL Bandwidth Allocation via CPE Speed Reversal Signal
Customer premise equipment sends a speed reversal signal to network devices for dynamic bandwidth allocation.
- DSP Timing Extraction for IP Network Synchronization
Digital signal processors extract timing from UDP streams, eliminating the need for expensive GPS receivers or reference boards in IP networks.
- Time Triggered Switch Schedule Consistency via Sparse Time Base
Storing active and new schedules in a switch enables consistent switching via a sparse time base, preventing phase jumps in periodic messages.
- Latency Determination in Substation Networks Using PTP
Precision Time Protocol messages carry timestamps through substation networks to calculate link latency without GPS hardware.
- NAT Device Characterization via STUN Probe Packets
Internal computers analyze STUN server responses to UDP probes, identifying NAT characteristics that prevent dropped packets during traversal.
- Ethernet Switch Timestamp Circuit Reduces Residence Time
Dedicated hardware timestamp circuits replace software processing to reduce residence time, thereby improving clock synchronization accuracy in gPTP networks.
- TCP Header Processing for Round-Trip Time Reduction
Early header processing enables transport layer acknowledgment transmission, reducing round-trip times and increasing throughput.
- Data Stream Modification Machine for Arbitrary Insertion and Removal
A programmable logic device modifies serial data streams by inserting or removing fixed-length data at specified points within words.
- Zone Routing Network Controller LSP Management
Hierarchical zone segmentation reduces hardware complexity and packet overhead by consolidating label-switched path creation at boundary nodes.
- Multimedia Packet Adaptation via Base Station Selection
Base station selects appropriate multimedia packet versions from source transmissions for mobile delivery.
- Dynamic Ethernet Clock Topology for Automotive Networks
ECUs dynamically determine clock sources using time synchronization protocols, resolving static network rigidity and improving latency.
- Dual-Slot MAC Protocol for Synchronous Asynchronous Node Coexistence
Segmenting time slots by duration allows synchronous and asynchronous nodes to coexist while minimizing packet collisions and interference.
- Time Synchronization Frame for Single-Line Resource Saving
A time synchronization frame carries a Time of Day field and coding identifier over one line to enable bidirectional device tracing.
- Clock Fault Detection in Synchronized Network Devices
Network devices detect poor clock signal quality via feedback mechanisms, downgrading indications to prevent synchronization degradation.
- ODUflex Lossless Bandwidth Adjustment via Tributary Slot Automation
Automated ODUflex bandwidth adjustment using downstream node tributary slot selection for lossless rate changes.
- Bus System Subscriber Timestamp Synchronization
A bus subscriber adjusts timestamp values in data packets to synchronize timers across the network.
- GFP Demapper Parallel Frame Delineation
A GFP framer generates core header candidates to delineate frame boundaries on wide data buses.
- Synchronized TDMA Network for Low Latency and Power Efficiency
Central control system assigns discrete time slots to computing devices, reducing idle power consumption while maintaining high data throughput.
- Secure UWB Ranging via MAC Layer Authentication and Delayed Response
A secure ultra wideband ranging protocol uses a media access control layer to authenticate devices before transmitting range packets with encrypted random delays.
- FlexE Shim Time Transfer via Dedicated Synchronization Channel
A FlexE shim carries Precision Time Protocol messages through a dedicated overhead channel to synchronize node clocks.
- LTE Wi-Fi Coexistence via Predictive Time Sharing
Predictive traffic pattern analysis enables application-aware time sharing between LTE and Wi-Fi interfaces, reducing adjacent channel interference.
- WiFi MAC Frame Memory Management via Chunk Segmentation
Segmenting shared memory into equal chunks resolves throughput bottlenecks from variable-sized MAC frames.
- Mobile Terminal Pre-Handover Address Acquisition
A mobile terminal requests link local addresses from a current access router before handover, resolving packet loss caused by delayed routing table updates.
- Service Multiplexing via Switching Indication Bit Blocks
Insert service switching indication bit blocks between streams to enable real-time dynamic service switching.
- Programmable Logic Device Integrating Framer Mapper and Processor
Integrating a framer, mapper, and embedded processor on a single programmable logic device reduces board space and electromagnetic interference.
- Reduced PCI Express Packet Headers for Burst Efficiency
Compressed packet headers omit unchanged fields during burst transactions, reducing bandwidth consumption and pin count requirements.
- FlexE Slot Group Sequence Embedding for Fast Link Establishment
Embedding sequence information within FlexE slot groups eliminates overhead frame delays, enabling rapid link establishment and dynamic rate switching.
- Bodily Sensation Multiplexing in Video Content Systems
Numeric conversion of sensitivity parameters enables precise synchronization between video scenes and external equipment, reducing communication line burdens.
- OFDMA Ranging Using FFT Reuse and Code Segmentation
Segment ranging codes and reuse FFT data to maintain accuracy at low SNR while reducing computational overhead.
- PLL Monitor Circuit for Radio Transceiver Frequency Lock
A phase lock loop monitor circuit detects frequency target failures and cycle slips to abort radio operations.
- Network Node Timing Adjustment for VoIP Latency Reduction
A network node adjusts transmission opportunity timing to synchronize with application data arrival patterns.
- TSCH Network Node Aggregates Routing Reports
Aggregated routing protocol reports reduce control traffic volume and packet losses in low power lossy networks.
- Network Device Automatic Protocol Detection for Multi-Platform Support
A network device senses signals at different rates to determine the networking protocol before enabling transmission.
- Ethernet Clock Synchronization via PTP Packet Distribution
Distributes time reference packets to synchronize intermediate devices, eliminating buffer dimensioning complexity and achieving sub-50 nanosecond jitter.
- Audio Network Master Device Zone Management
Master device polls wired and wireless audio slaves to aggregate state, reducing bandwidth while maintaining multi-room synchronization.
- Ethernet Timestamp Insertion via Type Field Detection
A reconciliation sublayer detects a type field value to insert a reception timestamp directly into an Ethernet data frame.
- Routing Information Base Priority Processing for Network Elements
Assigns priorities to routing information in a Routing Information Base before transferring data to a Forwarding Information Base.
- Block Repeating Spread Diversity Signal Transmission
Weighting factor sequences process data blocks into repeated units mapped to time-frequency positions for signal transmission.
- RF Ranging via Phase Difference and Clock Adjustment
A radio system adjusts a reference clock based on received signals to determine distance via phase difference, eliminating complex synchronization requirements.
- ODUk Subnet Connection Protection with Tandem Connection Monitoring
Allocates distinct TCM levels within nodes to resolve signal quality gaps across operator-managed subnets without complex end-to-end coordination.
- Serial Buffer Protocol Translation for sRIO and Lite Interoperability
A serial buffer translates packet headers between sRIO and Lite protocols to enable direct communication across different system interfaces.
- Digital Time Processing for TSN Phase Noise Reduction
Digital time processing applies rational number filters and time-to-digital converters to eliminate quantization errors in IEEE 1588 timing distribution.
- Egress Timestamp Generation Using Correction Factors
A timestamp generation system produces accurate egress timestamps using a correction factor derived from historical data.
- Duplexer-less Transceiver with Balancing Impedance Circuit
A duplexer-less transceiver uses a balancing impedance circuit to mimic antenna characteristics and enable on-chip integration.
- TDM Frame Transmission Using Ring Buffer Descriptors
Ring buffer descriptors segment TDM frames to eliminate large ping-pong buffers, reducing transmission delay and conserving link resources.