ETS Package Substrate with Raised Pillars for Dense Die Interconnects
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing integrated circuit (IC) packages face issues with metal consumption and cracking due to reduced-sized embedded trace substrate (ETS) interconnects, which can compromise the quality and integrity of die-to-die connections.
Innovation Solution
The implementation of raised metal pillar interconnects, which are formed above the ETS layer to provide increased volume and reduce metal consumption, allowing for smaller line-spacing ratios and higher connection density without cracking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional multi-layer PCB construction methods are used, then signal transmission quality can be maintained, but manufacturing complexity and production time increase significantly
Solution Approach 1:
The manufacturing process is segmented into distinct phases: forming recesses in the substrate, embedding conductive materials in the recesses, and selectively removing portions of the substrate. This segmentation allows each operation to be optimized independently while maintaining overall signal quality and reducing cumulative manufacturing complexity.
Solution Approach 2:
The invention transitions from traditional planar PCB construction to a three-dimensional substrate structure with recesses and embedded conductive materials. This dimensional change enables traces to be formed within the substrate volume rather than only on surfaces, reducing the number of layers needed and simplifying the interconnection architecture.
2Adaptability or versatility
If conventional PCB manufacturing processes are used, then design flexibility can be achieved, but production time and costs increase
Solution Approach 1:
Recesses are formed in the substrate before conductive materials are embedded, and selective removal of substrate portions is performed after trace formation. These preliminary and sequential actions enable design flexibility to be built into the manufacturing process itself, allowing different trace patterns and configurations to be produced without retooling while maintaining efficient production flow.
3Adaptability or versatility
If substrate material is removed to form traces, then trace routing flexibility improves, but structural integrity may be compromised
Solution Approach 1:
Conductive materials are nested within recesses formed in the substrate, creating a hierarchical structure where traces are embedded rather than removed. This nesting approach provides trace routing flexibility while the surrounding substrate material maintains structural integrity, as the substrate forms a continuous matrix that supports the embedded conductive elements.
Solution Approach 2:
The invention creates a composite structure combining substrate material and embedded conductive materials. This composite approach allows trace routing flexibility through selective removal and embedding operations, while the combination of materials provides both electrical functionality and structural strength, with the substrate acting as a reinforcing matrix.
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
Integrated circuit (IC) package substrate with an embedded trace substrate (ETS) layer on a substrate, and related fabrication methods. The package substrate of the IC package includes an ETS layer provided on the substrate to facilitate providing higher density substrate interconnects to provide bump/solder joints for coupling a semiconductor die to the package substrate. ETS interconnects in the ETS layer in the package substrate facilitates die connections having a reduced line-spacing ratio (L/S) (e.g., 5.0 micrometers (µm)/5.0 µm or less) over substrate interconnects in a substrate. In additional exemplary aspects, raised metal pillar interconnects are formed in contact with respective ETS interconnects of the ETS layer of the package substrate to avoid or reduce metal consumption by die solder disposed on metal pillar interconnects of the ETS layer providing bump/solder joints.