ETSOI Extension Resistance Reduction via Raised S/D
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Solution Overview
Problem
High extension resistance in extremely thin silicon-on-insulator (ETSOI) semiconductor devices limits their application to high-performance logic devices due to increased transistor engineering complexity and degradation issues with metal gate electrodes during high-temperature annealing.
Innovation Solution
The method involves forming an SOI substrate with a thin silicon layer, epitaxially growing a silicon-containing layer, and replacing the gate electrode with a high-k metal gate, while forming raised and faceted source/drain regions to reduce extension resistance and improve short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ETSOI is thinned to improve short channel control, then short channel effects are improved, but extension resistance increases
Solution Approach 1:
The patent applies local quality by forming a lightly-doped extension region with a different doping concentration than the heavily-doped source/drain regions. The extension region has a doping concentration of 1E18 to 1E20 atoms/cm³, while source/drain regions have 1E19 to 1E21 atoms/cm³. This localized doping variation reduces extension resistance in the thin ETSOI region without compromising short channel control, as each region is optimized for its specific function.
Solution Approach 2:
The patent introduces a vertical dimension solution by forming raised source/drain regions that extend upward from the ETSOI surface. This three-dimensional structure allows current to flow through multiple paths (through the thin ETSOI and through the raised regions), effectively reducing extension resistance without increasing the lateral dimensions or compromising the thin ETSOI thickness needed for short channel control.
2Power
If metal gate electrode is used to improve drive current, then drive current increases, but degradation occurs during high-temperature annealing
Solution Approach 1:
The patent applies preliminary action by forming the metal gate electrode before the high-temperature annealing process. The gate electrode is deposited and patterned prior to source/drain implantation and annealing steps. This sequencing allows the metal gate to be in place during drive current enhancement while the subsequent annealing processes are optimized to minimize gate degradation through controlled temperature profiles and atmospheric conditions.
Solution Approach 2:
The patent employs parameter changes by carefully controlling annealing temperature, time, and atmospheric conditions to reduce metal gate degradation. The annealing process is optimized to activate source/drain implants while maintaining gate electrode integrity through parameter adjustment, such as using nitrogen or forming gas atmospheres and controlling peak temperatures to prevent excessive gate diffusion or reaction.
3Power
If polysilicon gate is replaced with metal gate to reduce depletion, then drive current improves, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the gate structure into multiple functional layers: a metal gate layer for high drive current, a gate dielectric layer for electrical isolation, and a capping layer for protection. This segmented approach allows each layer to be optimized independently and simplifies the overall manufacturing process by using standard deposition and patterning techniques for each layer rather than requiring complex monolithic gate structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes ETSOI thickness loss, reduces extension resistance, and enhances short channel control, making ETSOI suitable for high-performance logic devices beyond the 22 nm node.
Implementation Method 1
epitaxially forming a silicon-containing layer on the SOI substrate
Data Source
AI summary
A semiconductor is formed on an SOI substrate, such as an extremely thin SOI (ETSOI) substrate, with increased extension thickness. Embodiments include semiconductor devices having an epitaxially formed silicon-containing layer, such as embedded silicon germanium (eSiGe), on the SOI substrate. An embodiment includes forming an SOI substrate, epitaxially forming a silicon-containing layer on the SOI substrate, and forming a gate electrode on the epitaxially formed silicon-containing layer. After gate spacers and source/drain regions are formed, the gate electrode and underlying silicon-containing layer are removed and replaced with a high-k metal gate. The use of an epitaxially formed silicon-containing layer reduces SOI thickness loss due to fabrication process erosion, thereby increasing extension thickness and lowering extension resistance.