Extended Bit Line Precharge Using Balancing Circuits
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in accessing word-lines efficiently using bit lines due to limitations in precharge timing and physical length, which affects the read operation of memory cells.
Innovation Solution
The implementation of extended bit lines that precharge from both ends, utilizing balancing circuits to connect bit lines to a precharging source, allowing longer bit lines while maintaining precharge timing requirements, thereby enabling flexible circuit layouts and increased memory cell density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If bit lines are extended to access more word-lines, then memory cell density and circuit layout flexibility are improved, but precharge timing requirements are violated due to increased propagation delay
Solution Approach 1:
The bit line precharge operation is segmented into two independent directions: one from the first end and another from the second end. Balancing circuits are placed at both ends of the extended bit lines, allowing simultaneous bidirectional precharging. This segmentation reduces the propagation delay from one end to meet the precharge timing requirement while maintaining extended bit line length for higher memory cell density.
2Quantity of substance
If bit lines are extended to increase memory cell density, then the number of accessible memory cells increases, but propagation delay increases violating timing constraints
Solution Approach 1:
The precharge operation is divided into two concurrent segments traveling in opposite directions from respective ends of the bit line. The balancing circuits at both ends initiate precharge signals simultaneously, effectively halving the propagation delay compared to unidirectional precharging, thereby allowing extended bit lines to access more memory cells without violating timing constraints.
Solution Approach 2:
The balancing circuits at both ends of the extended bit lines perform preliminary precharging actions before the memory read operation begins. By precharging the extended bit line segments from both ends in advance, the system ensures that the bit lines are ready for data sensing without incurring additional delay during the actual read operation, thus maintaining timing constraints while supporting extended bit line length.
Data Source
AI summary
Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.