Transistor TRIZ Cases

Source and drain regions apply tensile stress to the conductive oxide channel layer, reducing leakage current while maintaining high on-current characteristics.

Segmented isolation structures with buried trench silicide features reduce parasitic capacitance by providing electrical isolation near gate electrodes.

A multigate ESD protection field effect transistor with a partially depleted charge carrier structure modulates trigger voltage to safeguard functional circuits.

A replacement gate structure with a sacrificial layer enables flexible fin height adjustments in semiconductor manufacturing.

A semiconductor device uses overlapping transparent electrodes to form a storage capacitor within the pixel structure.

Plasma-activated nitridation forms a nitride layer on the substrate to reduce voids and enhance carrier mobility.

Lateral SOI devices embed permanent charge in drift region insulation to balance electrical fields.

Segmented gate electrodes apply non-inverting voltages to diode regions, reducing conduction loss while maintaining breakdown voltage.

Surrounding gate insulation with a conductive layer connects neighboring pillars, reducing resistance and preventing pattern collapse.

A two-step inner spacer method forms multiple work function gate stacks in nanosheet transistors without metal patterning.

Segmenting the device allows independent channel dimensioning to reduce on-state resistance while increasing packing density.

A stacked silicon controlled rectifier uses a resistor to link internal portions of two transistors, doubling the holding voltage while maintaining single-level triggering.

Selective epitaxial base regions enable tailored collector and base doping profiles on a single wafer using patterned oxide masks.

Strategic third spacer placement on the second gate top surface resolves inconsistent metal silicide formation, enhancing yield and reliability.

Back-side illuminated image sensor uses doped regions at varying depths to absorb blue light, resolving low-light sensitivity issues in downscaled CMOS sensors.

One mask forms source drain and lightly doped areas in a TFT array substrate, eliminating extra mask design costs while controlling LTPS leakage current.

A high voltage driver circuit clamps the gate voltage of a high-side transistor using a differential to single-ended converter and translator.

Bidirectional precharging via balancing circuits reduces propagation delay to maintain timing constraints for extended bit lines.

An epitaxial layer fills a recessed substrate under the gate stack to induce strain while preventing germanium oxide formation.

A protrusion with a concave-convex structure defines the gap between electrodes to precisely control channel size in active device substrates.

A semiconductor integrated circuit device uses a cavity and p-type diffusion region to extract charge carriers from the substrate.

A patterned first insulating layer with varying thickness compensates for signal attenuation in array substrates.

Segmenting the semiconductor layer into multiple parallel islands reduces threshold voltage shifts caused by positive bias stress in display applications.

Multi-trench isolation structures use bias arrangements to divide voltage, reducing thermal destruction and improving reliability in high-voltage applications.

Inverted silicon nitride and oxide layers with a constrained trench prevent copper oxidation, resolving reliability trade-offs in oxide TFT manufacturing.

Mandrel structures decouple gate width from fin sidewall angles, eliminating stringer defects that cause short circuits.

Integrated circuit system monitor detects minor ESD damage via leakage current measurement, enabling early quality control without disrupting normal operation.

Sloped contact etch stop layer spacers guide pre-metal dielectric deposition to eliminate voids in high aspect ratio openings.

Opposing internal stress in alternating oxide semiconductor layers balances mechanical forces, preventing warpage and enabling high integration density.

A voltage detector uses a reference voltage generator with floating gate MOS transistors to produce an adjustable threshold.

A semiconductor device uses an oxide semiconductor film with conductive pillars to enhance switching characteristics and integration density.

Offset adjacent structures parallel to cell borders to form non-identical unit pairs, resolving design rule conflicts without increasing array area.

A photosensitive field-effect transistor uses a semiconducting layer with vertically stacked assemblies of different work functions to funnel charge carriers.

Direct metal-to-source connections eliminate contact structures in SGT CMOS inverters, reducing power supply line resistance and delay time.

A solid state power controller regulates current flow using thermal thresholds to manage pre-charge phases.

A driving circuit uses a series resistance network to suppress crosstalk noise in high-speed optical modules.

Dummy gate structures limit lateral extent of raised source and drain regions, preventing electrical shorts between neighboring semiconductor fins.

Segmented offset insulating layers improve breakdown voltage and reduce leakage current without requiring additional mask processes.

A semiconductor structure uses a composite layer with an inside wall to support the channel laminated layer and prevent mechanical collapse.

Gradient impurity profiles in DMOS regions control source-drain breakdown voltage, resolving substrate uniformity issues without complex trench formation.

An electrostatic discharge protection circuit uses an RC network and switch transistor to control voltage levels at the input terminal.

Selective laser annealing activates implanted dopants at precise temperatures, eliminating complex masking steps and reducing manufacturing costs.

Segmenting silicon circuitry and magnetic material into separate dies reduces parasitic inductances while maintaining compact component dimensions.

A vertical junction field effect transistor uses a thin semiconductor gate grown on channel sidewalls to reduce input capacitance.

Segmented fin-shaped emitter, base, and collector regions reduce the large area of stationary base and collector regions in conventional designs.

A thin-film transistor uses a transparent conductive layer to electrically connect the source electrode and active layer.

Nested terminal portions with inclined surfaces reduce Hall element module volume while preventing detachment from the resin package.

Selective etching removes second features faster than first materials, reducing edge placement errors in sub-30 nm FinFETs.

A one-transistor DRAM cell uses a quantum well structure to store charge without a capacitor.