Semiconductor Pillar Gate Insulation Conductive Layer Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The reduction in semiconductor device design rules leads to decreased unit memory cell dimensions, resulting in increased resistance and decreased transmission efficiency of driving voltage in upper/lower channel transistors due to the collapse of photoresist patterns and insufficient contact area between the line pattern and gate electrode, affecting the reliability and stability of the device.
Innovation Solution
A semiconductor device with pillar patterns, a gate insulation layer, and a conductive layer that surrounds the gate insulation layer and connects neighboring gate electrodes, forming a wordline that functions as both a gate electrode and a line, thereby increasing the transmission efficiency of driving voltage and preventing pillar pattern collapse through a trimming process that maintains a width of 50 nm or less.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the photoresist pattern width is reduced to 50 nm or less to meet design rule requirements, then the unit memory cell dimension decreases, but the photoresist pattern collapses and the pillar pattern width cannot be maintained
Solution Approach 1:
The gate electrode is divided into two separate layers: a first conductive layer (polysilicon) and a second conductive layer (metal). This segmentation allows the gate electrode to be formed in two distinct deposition steps, enabling the pillar pattern width to be precisely controlled at 50 nm or less without photoresist collapse, while still achieving the required unit memory cell dimension reduction.
Solution Approach 2:
The invention transitions from a single-layer gate electrode to a two-layer gate electrode structure. This dimensional change in the gate electrode's construction (adding a vertical layer dimension) enables simultaneous achievement of narrow pillar patterns (≤50 nm) and proper gate electrode formation, resolving the contradiction between miniaturization and manufacturing precision.
2Device complexity
If the line pattern and gate electrode are formed as separate conductive materials, then the transistor structure is achieved, but the resistance increases and transmission efficiency of driving voltage decreases
Solution Approach 1:
The line pattern and gate electrode are merged into a single integrated conductive structure formed by the two-layer gate electrode. The first conductive layer extends to form both the gate electrode and the line pattern, eliminating the need for separate conductive materials and their associated contact resistance, thereby improving transmission efficiency while maintaining transistor structure.
Solution Approach 2:
The first conductive layer serves multiple functions: it forms the gate electrode for the transistor and simultaneously forms the line pattern for voltage transmission. This multi-functionality eliminates the need for separate conductive materials, reducing overall resistance and improving driving voltage transmission efficiency.
3Device complexity
If the contact area between the line pattern and gate electrode is insufficient, then the transistor is formed, but the contact resistance increases and overall resistance increases
Solution Approach 1:
The line pattern and gate electrode are merged into a continuous first conductive layer, eliminating the interface between separate conductive materials. This merging removes the contact resistance issue entirely, as there is no separate contact interface, while still achieving proper transistor formation.
Solution Approach 2:
The problematic contact interface between separate line pattern and gate electrode conductive materials is extracted/eliminated by forming them as a single continuous first conductive layer. This removes the source of contact resistance while maintaining the necessary transistor structure.
Data Source
AI summary
A semiconductor device includes pillar patterns, a gate insulation layer surrounding the pillar patterns, and a conductive layer surrounding the gate insulation layer and connects neighboring gate insulation layers.