High-Side Output Transistor Circuit Gate Voltage Clamping
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High voltage drivers, particularly those using PMOS transistors, face issues with gate oxide stress due to excessive voltage, leading to suboptimal operation and potential damage, along with issues like crowbar currents and incomplete switching at low temperatures.
Innovation Solution
A high voltage driver circuit incorporating a differential to single-ended (D2SE) converter and a high voltage translator, which supplies a first and second supply voltage to clamp the gate voltage of the high-side transistor, preventing gate oxide stress and eliminating crowbar currents by ensuring proper switching and reducing threshold voltage impact.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied to the gate of the PMOS transistor to increase over-drive capability, then the switching performance is improved, but the gate oxide becomes stressed and susceptible to damage
Solution Approach 1:
A high voltage translator circuit is introduced as an intermediary between the control logic and the PMOS transistor gate. This translator includes voltage clamping circuitry that limits the maximum gate voltage to a safe level (VDDIO - VPOSM), preventing gate oxide stress while still enabling adequate over-drive capability for proper transistor switching operation
Solution Approach 2:
The gate voltage parameter is dynamically controlled and clamped within a safe operating range. The high voltage translator modifies the voltage parameter by subtracting a offset voltage (VPOSM) from the supply voltage (VDDIO), ensuring the gate voltage never exceeds safe thresholds while maintaining sufficient over-drive for switching performance
2Power
If traditional high voltage driver circuits are used, then the circuit can drive high voltage outputs, but crowbar currents occur and low voltage transistors are damaged during power off conditions
Solution Approach 1:
Protective circuitry is built into the high voltage translator to preemptively prevent crowbar currents. The voltage clamping mechanism and controlled switching architecture actively oppose the formation of harmful current paths between supply rails, protecting low voltage transistors from damage during power off conditions while maintaining high voltage driving capability
3Reliability
If the gate voltage is clamped to prevent over-stress, then the gate oxide is protected, but the over-drive capability is reduced
Solution Approach 1:
The gate voltage is clamped to a specific parameter value (VDDIO - VPOSM) that represents the optimal compromise between protection and performance. This parameter change ensures the voltage is high enough to provide adequate over-drive capability for switching while remaining below the threshold that would cause gate oxide stress or damage
Data Source
AI summary
A high voltage driver includes a high-side output transistor circuit, a differential to single-ended (D2SE) converter connected to a gate of the high-side output transistor circuit, wherein the D2SE is supplied by a first and a second supply voltage, and a high voltage translator connected to the D2SE converter. The D2SE converter and the translator circuit are used to clamp a voltage at the gate of the high-side transistor circuit to be the first supply voltage less the second supply voltage.