SiC DMOS Transistor Segmentation for Resistance and Density
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Solution Overview
Problem
In silicon carbide-based DMOS transistors, the resistance component of the MOS field-effect transistor increases, affecting the on-state resistance and packing density due to the smaller electron drift speed and channel mobility compared to silicon, limiting the independent dimensioning of channel dimensions.
Innovation Solution
The semiconductor device decouples the MOS field-effect transistor and junction field-effect transistor by arranging them in separate semiconductor regions, allowing independent dimensioning of channel lengths and widths, and configuring them in a stripe structure to reduce the channel length and increase packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel dimensions are reduced to decrease on-state resistance, then the on-state resistance decreases, but the packing density increases excessively making independent dimensioning difficult
Solution Approach 1:
The patent divides the DMOS transistor into two separate functional regions: a first lateral semiconductor region containing the MOS field-effect transistor and a second lateral semiconductor region containing the junction field-effect transistor. This segmentation allows independent dimensioning of channel lengths and widths for each transistor type, enabling optimization of on-state resistance without being constrained by packing density issues in a unified structure.
2Reliability
If the channel length is reduced to improve performance, then the on-state resistance decreases, but the manufacturing precision requirements increase
Solution Approach 1:
By separating the MOS FET and junction FET into different semiconductor regions, the patent enables independent optimization of channel dimensions. The MOS FET channel length can be reduced to decrease on-state resistance while the junction FET can be designed with appropriate dimensions to compensate and maintain overall device performance, thereby reducing the stringency of manufacturing precision requirements for any single channel.
Data Source
AI summary
A semiconductor device is disclosed. One embodiment provides a top surface. A first lateral semiconductor region is arranged adjacent to the top surface and includes a transistor structure. The transistor structure includes a drain zone of a first conductivity type. A second lateral semiconductor region is arranged below the first semiconductor region and includes a junction field-effect transistor structure. The junction field-effect transistor structure includes a source zone of the first conductivity type which is electrically connected to the drain zone of the transistor structure.