Two-Step Inner Spacer for Multi-Vt Nanosheet Gate Stacks
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Solution Overview
Problem
Conventional methods struggle to achieve multiple work function gate stacks in nanosheet devices due to limited space between sheets, leading to organic planarization layer pinch-off and difficulties in metal patterning, which restricts the scaling of nanosheet transistors, especially for high-voltage applications.
Innovation Solution
A two-step inner spacer method is employed to form multiple work function gate stacks without metal gate patterning, where the first spacer is selectively formed on high-Vt devices, allowing for modulation of threshold voltages under the inner spacer, and the dipole layer stack is deposited without metal patterning, enabling multi-Vt devices with uniform sheet-to-sheet spacing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional metal gate patterning is used in nanosheet devices, then multiple work function gate stacks can be formed, but the limited space between sheets causes organic planarization layer pinch-off and manufacturing difficulties
Solution Approach 1:
The gate stack is segmented into multiple work function regions by forming inner spacers that divide the gate dielectric into separate regions. This segmentation allows different work function metals to be deposited in different regions without requiring complex patterning steps, as the spacers naturally define the boundaries between regions with different electrical characteristics.
Solution Approach 2:
Inner spacers are introduced as intermediary structures between the nanosheet channels and the gate metal layers. These spacers serve as physical barriers that prevent the organic planarization layer from pinching off and provide a foundation for selective work function metal deposition, eliminating the need for difficult metal gate patterning in the limited space between sheets.
2Productivity
If device spacing is reduced for scaling, then device density increases, but the space between sheets becomes too limited for conventional gate patterning processes
Solution Approach 1:
Inner spacers are formed preliminarily before metal gate deposition to pre-establish the structural framework needed for multiple work function regions. This preliminary action creates the necessary space and structural definition early in the process, enabling subsequent metal deposition without requiring complex patterning steps in the limited space between closely-spaced nanosheets.
Solution Approach 2:
The solution moves from planar patterning in the horizontal dimension to vertical structure formation using inner spacers. By utilizing the vertical dimension to create stacked inner spacer structures, the patent enables multiple work function regions without requiring additional horizontal patterning steps, thus accommodating reduced device spacing.
3Reliability
If thicker gate dielectric is used for higher voltage operation, then device reliability improves, but allowable device dimensions are further limited
Solution Approach 1:
The gate dielectric structure exhibits local quality variations through the inner spacer configuration, where different regions have different effective dielectric thicknesses and work function characteristics. This allows the device to accommodate thicker gate dielectric for high-voltage operation in specific regions while maintaining overall compact dimensions through the localized structural modifications provided by the inner spacers.
Data Source
AI summary
A method is presented for selective dipole layer modulation. The method includes forming a nanosheet stack over a substrate, the nanosheet stack including alternating layers of a first semiconductor material, a second semiconductor material, and a third semiconductor material, etching the first and second semiconductor materials to define indentations, forming first inner spacers within the indentations, removing residual of the first semiconductor material, forming second inner spacers adjacent the first inner spacers, removing the remaining first and second semiconductor materials to define openings adjacent the first inner spacers, and filling the openings with a dipole layer stack to create multiple work function gate stacks with multiple threshold voltages (Vt) without metal gate patterning due to pinch-off exhibited between the first inner spacers and a nanosheet channel.