One-Transistor DRAM Cell with Quantum Well Structure
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Solution Overview
Problem
Conventional DRAM scaling is hindered by the large area occupied by capacitors and limited material integration with silicon, leading to difficulties in reducing cell size and improving retention time and read current margin in one-transistor dynamic random access memory (1T DRAM) devices.
Innovation Solution
A 1T DRAM cell with a quantum-well structure using a heterojunction on a bulk silicon substrate, where a quantum well is formed between semiconductor layers with different materials, allowing for charge storage and enabling low-power, high-speed operation through gate-induced drain leakage or band-to-band tunneling, without the need for a capacitor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional 1T1C DRAM cell structure is used, then charge storage is achieved through a capacitor, but the device area becomes large and scaling is limited
Solution Approach 1:
The patent extracts the charge storage function from the conventional capacitor component and relocates it to a quantum well structure formed within the semiconductor body region. This eliminates the need for a separate capacitor, thereby reducing cell area while maintaining charge storage capability through quantum confinement effects in the heterostructure
Solution Approach 2:
The patent transitions from planar charge storage in a capacitor to three-dimensional quantum well confinement within the vertical heterostructure of the body region. The quantum well is formed by stacking semiconductor layers with different band gaps vertically, creating charge storage in the depth dimension rather than lateral expansion
2Reliability
If capacitor scaling is attempted by increasing dielectric constant or aspect ratio, then charge storage density improves, but manufacturing complexity and process requirements increase
Solution Approach 1:
The patent changes the fundamental parameter of charge storage from capacitive electric field storage to quantum mechanical confinement storage. By altering the band gap parameter through material composition in the heterostructure, charge storage is achieved through quantum well formation rather than high-k dielectric scaling, simplifying manufacturing requirements
Solution Approach 2:
The patent employs composite semiconductor heterostructures with different band gap materials (e.g., Si/SiGe or GaAs/AlGaAs) to form the quantum well. This composite material approach enables charge storage through material property differences rather than geometric scaling, reducing manufacturing complexity
3Area of stationary object
If 1T DRAM devices are made on SOI substrates to reduce cell size, then area is reduced, but retention time and read current margin deteriorate
Solution Approach 1:
The patent applies local quality by creating a specific heterostructure region within the body with enhanced charge confinement properties. The quantum well is localized in the drain-side body region with tailored band gap engineering, providing strong charge storage locally while maintaining overall device functionality and improving retention characteristics
4Area of stationary object
If channel length is reduced for scaling, then device area decreases, but charge storage capability and retention time worsen
Solution Approach 1:
The patent compensates for reduced channel length by moving charge storage to the vertical dimension through quantum well confinement in the body heterostructure. The quantum well provides three-dimensional charge confinement independent of channel length, enabling area reduction through channel scaling without sacrificing storage capability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution reduces the device area, enhances retention time, and increases read current margin, enabling operation in harsh environments, including high temperatures, while utilizing conventional CMOS technology to maintain scalability.
Implementation Method 1
a quantum well is formed between semiconductor layers with different materials, allowing for charge storage
Implementation Method 2
enabling low-power, high-speed operation through gate-induced drain leakage or band-to-band tunneling
Implementation Method 3
a first heterojunction surface formed between a first semiconductor layer and a second semiconductor layer perpendicular to the channel length direction
Data Source
AI summary
A 1T DRAM cell device having two or more heterojunction surfaces perpendicular to the channel length direction and a quantum well at the drain region side. The 1T DRAM cell device described herein may be driven by GIDL or band-to-band tunneling, so that low voltage and high speed operation can be performed, and retention time and read current margin can be dramatically increased. It can also be driven as a memory device in harsh environments with high temperatures. Furthermore, since the heterojunction surfaces can be formed by vertically stacking epitaxial layers on a semiconductor substrate such as silicon, the conventional CMOS process technology can be used, and the area occupied by the device can be reduced as much as possible without limiting the channel length.