Semiconductor Integrated Circuit Device With Cavity Hole Extraction
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Solution Overview
Problem
High side drive circuits in semiconductor integrated circuits face malfunctions and increased chip size due to negative surges, which are not effectively addressed by existing solutions such as p-type impurity regions or high voltage diodes, leading to issues like hole implantation and latch-up during high voltage operations.
Innovation Solution
A semiconductor integrated circuit device with a cavity between the high side drive circuit and the low potential region, and a p-type diffusion region penetrating to the cavity, which extracts holes and prevents punch-through, reducing the interval between the high side drive circuit and the n++ type region, thereby minimizing chip size and preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a p-type impurity region or high voltage diode is used to address negative surges, then hole extraction is improved, but chip size increases
Solution Approach 1:
The patent introduces a cavity structure that extends in the depth dimension (z-direction) to reach the punch-through region, allowing hole extraction without increasing the planar chip area. The cavity provides a three-dimensional pathway for hole collection while maintaining a compact two-dimensional footprint.
Solution Approach 2:
The patent introduces a n-type region as an intermediary structure between the p-type impurity region and the punch-through region. This n-type region acts as a mediator to enhance hole extraction efficiency while controlling the electrical characteristics and preventing direct interaction between conflicting doped regions.
2Area of stationary object
If the interval between the high side drive circuit and the n++ type region is reduced, then chip size is minimized, but hole implantation and latch-up risks increase
Solution Approach 1:
The patent extracts holes from the harmful path by introducing a p-type impurity region with a cavity that reaches the punch-through region. This creates a dedicated hole collection pathway that removes holes before they can cause latch-up or implantation in the high side drive circuit, allowing safer reduction of the interval.
Solution Approach 2:
The patent converts the harmful negative surge that causes hole implantation into a beneficial effect by using the same surge to drive holes into the p-type impurity region through the cavity, where they are safely collected. The harmful holes are redirected from damaging the high side drive circuit to being utilized for safe extraction.
3Strength
If existing solutions are used to prevent punch-through, then breakdown voltage is maintained, but device complexity increases
Solution Approach 1:
The cavity structure serves multiple functions simultaneously: it enables hole extraction, maintains breakdown voltage by reaching the punch-through region, and allows interval reduction for compact design. This multi-functional structure eliminates the need for separate components, reducing overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively reduces hole implantation and prevents chip size increase, ensuring stable operation even under high load currents and large floating inductance, while maintaining a sufficient breakdown voltage and preventing substrate punch-through.
Implementation Method 1
a p-type diffusion region penetrating to the cavity, which extracts holes and prevents punch-through
Data Source
AI summary
An MV-PMOS and MV-NMOS configuring a high side drive circuit are formed in an n-type isolation region formed on a p-type semiconductor substrate. The MV-NMOS is connected to a p-type isolation region of an intermediate potential in the interior of the n-type isolation region. An n-type epitaxial region is provided in a surface layer of the p-type semiconductor substrate on the outer side of the n-type isolation region, and a p-type GND region of a ground potential (GND) is provided on the outer side of the n-type epitaxial region. A cavity is provided between the p-type semiconductor substrate and n-type epitaxial region between the high side drive circuit and p-type GND region, and a p-type diffusion region is provided penetrating the n-type epitaxial region and reaching the cavity. The intermediate potential is applied to the p-type isolation region.