FinFET Channel Stability via Composite Inside Wall Support
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Solution Overview
Problem
As semiconductor manufacturing advances with smaller characteristic dimensions, the short-channel effect (SCE) becomes more prevalent due to reduced channel lengths in MOSFETs, leading to subthreshold leakage and poor gate control, which traditional planar MOSFETs struggle to mitigate effectively.
Innovation Solution
The method involves forming a semiconductor structure with discrete fins and channel laminated layers, including an initial sacrificial layer and channel layer, where the sacrificial layer is etched to create a groove and through groove, and a composite layer with a first inside wall is formed to provide support for the channel layer, stabilizing it against deformation or collapse.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the channel length is reduced to adapt to smaller characteristic dimensions, then the device can be scaled down, but the gate control capability deteriorates and subthreshold leakage increases
Solution Approach 1:
The patent transitions from a planar MOSFET to a three-dimensional FinFET structure. The channel is formed as a vertical fin extending from the substrate, allowing the gate to control the channel from three sides (top and two lateral sides). This dimensional change enables effective gate control even with reduced channel lengths by utilizing the vertical dimension and multi-sided gate coverage.
Solution Approach 2:
The channel layer is segmented into multiple thin laminated layers stacked vertically. This segmentation allows each layer to be independently controlled by the gate, improving overall gate control capability. The segmented structure also reduces the effective channel length for each segment while maintaining the total channel depth, thereby mitigating short-channel effects.
2Productivity
If the channel length is reduced, then device scaling is achieved, but short-channel effects and subthreshold leakage worsen
Solution Approach 1:
By forming the channel as a vertical fin structure extending from the substrate surface, the patent utilizes the vertical dimension to maintain effective gate control. The gate wraps around the fin from three sides, creating a three-dimensional control geometry that suppresses short-channel effects even as the horizontal characteristic dimensions are reduced for device scaling.
Solution Approach 2:
The channel structure employs composite materials including the fin material (e.g., silicon), channel layer materials (e.g., SiGe, III-V族半导体), and gate dielectric materials. This composite structure allows optimization of each layer's properties to maintain effective mass and carrier control while suppressing short-channel effects, enabling continued device scaling.
3Ease of manufacture
If a planar MOSFET structure is used, then manufacturing is simpler, but gate control capability is insufficient for reduced channel lengths
Solution Approach 1:
The patent adopts a three-dimensional FinFET structure where the channel is formed as a vertical fin and the gate controls it from three sides. This dimensional change provides superior gate control capability compared to planar MOSFETs, while the fabrication process builds upon existing CMOS manufacturing techniques, making the transition feasible despite the increased structural complexity.
4Reliability
If the channel layer is made longer to improve gate control, then short-channel effects are suppressed, but channel stability and resistance to deformation decrease
Solution Approach 1:
The channel layer is divided into multiple thin laminated layers stacked vertically. This segmentation provides structural support to each individual layer, preventing deformation and collapse that would occur in a single long channel. Each thin layer is mechanically stable while collectively forming a longer effective channel for improved gate control.
Solution Approach 2:
The channel structure uses composite materials with different mechanical and electrical properties. The fin material provides structural support, while the channel layer materials (e.g., SiGe, III-V族半导体) are deposited as thin laminated layers that are mechanically stable. This composite construction maintains channel stability even with increased channel length for better gate control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical performance of the semiconductor structure by maintaining channel stability and improving gate control, even with longer channel layers, thereby optimizing the semiconductor's efficacy.
Implementation Method 1
etching the initial sacrificial layer along an extension direction perpendicular to the initial channel laminated layer, to form a first groove encircled by the initial channel layer
Implementation Method 2
a residual initial channel laminated layer located on the fin is used to form a channel laminated layer, the channel laminated layer includes a composite layer and a channel layer located on the composite layer, and the composite layer includes a first inside wall and a sacrificial layer located on a sidewall of the first inside wall
Data Source
AI summary
Disclosed are a semiconductor structure and a method for forming same. A forming method includes: forming a first inside wall in a first groove; etching an initial channel laminated layer and an initial fin after the first inside wall is formed, where the residual initial fin is used as a fin, and the residual initial channel laminated layer located on the fin is used to form a channel laminated layer, the channel laminated layer includes a composite layer and a channel layer located on the composite layer, and the composite layer includes a first inside wall and a sacrificial layer located on a sidewall of the first inside wall; forming a pseudo gate structure across the channel laminated layer after the fin is formed; forming a source-drain doping layer in channel laminated layers on two sides of the pseudo gate structure; and removing the pseudo gate structure and the sacrificial layer after the source-drain doping layer is formed, and forming a metal gate structure at positions of the pseudo gate structure and the sacrificial layer. The first inside wall provides support for the channel layer. Therefore, even though the channel layer is relatively long, the channel layer cannot easily deform or collapse under the gravity effect, thereby optimizing the electrical performance of the semiconductor structure.