FinFET Gate Isolation Structures for Parasitic Capacitance Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In FinFET semiconductor devices, close proximity of contacts to gate electrodes leads to insufficient electrical isolation, resulting in parasitic capacitance that degrades device performance and increases effective capacitance, hindering the reduction of device dimensions and overall chip performance.
Innovation Solution
The implementation of improved isolation structures and processing methods, including the formation of buried trench silicide features with reduced depth and the use of high-K dielectric materials as contact etch-stop layers, to minimize parasitic capacitance and enhance the selectivity of epitaxial features, thereby reducing effective capacitance and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If contacts are placed close to gate electrodes to reduce device dimensions, then device scaling is improved, but parasitic capacitance increases and electrical isolation deteriorates
Solution Approach 1:
An isolation structure comprising a trench filled with dielectric material is introduced between the contact and the gate electrode. This intermediary structure provides electrical isolation while allowing the contact to remain in close proximity to the gate electrode, thus enabling device scaling without significant parasitic capacitance penalty.
Solution Approach 2:
The isolation structure is segmented into multiple components: a trench structure separating the contact from the gate electrode, and a conductive structure that bridges portions of the gate electrode while being electrically isolated from the contact. This segmentation allows independent optimization of electrical connection and isolation.
2Object-affected harmful factors
If isolation structures are introduced to reduce parasitic capacitance, then electrical isolation is improved, but device complexity increases
Solution Approach 1:
The isolation structure serves multiple functions simultaneously: it provides electrical isolation between the contact and gate electrode to reduce parasitic capacitance, and the conductive structure within it provides electrical connection between different portions of the gate electrode. This multi-functionality reduces the need for separate structures.
Solution Approach 2:
The isolation structure and the gate electrode connection structure are merged into a single integrated component. The conductive structure is embedded within the dielectric material of the isolation structure, combining isolation and conduction functions in one element, thereby reducing overall device complexity.
Data Source
AI summary
A semiconductor device, comprising first and second sets of fins; first and second gate electrodes; first and second isolation structures each separating one of the gate electrodes into a first portion and a second portion; and first and second conductive structures wider than the corresponding isolation structure and disposed on an entirety of a top of the corresponding isolation structure and on a part of the top of each of the first and second portions of the corresponding gate electrode. A method for making the semiconductor device. A system configured to implement the method and manufacture the semiconductor device. The semiconductor device may have a low parasitic capacitance and high chip performance.