External Memory Storage for Semiconductor Test Repair Data

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Solution Overview

Problem

The limited memory space in Automatic Test Equipment (ATE) for semiconductor devices leads to insufficient storage for defect and repair information, resulting in increased test costs and reduced efficiency, especially when testing large-capacity memories or requiring precise analysis.

Innovation Solution

A memory test method that utilizes additional memories outside the ATE to store repair information, allowing for increased storage capacity without expanding the ATE's internal memory, thereby reducing the need for multiple repairs and speeding up the testing process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the memory space of the ATE is increased to store defect information and repair information, then the storage capacity is improved, but the cost of the ATE increases significantly

Engineering Contradiction:
Improvestorage capacityVSAvoidcost
Core Design Contradiction:
Quantity of substanceVSEase of manufacture

Solution Approach 1:

The patent introduces an external memory device as an intermediary between the ATE and the memory under test. The external memory stores defect information and repair information that would otherwise require large ATE memory capacity. This mediator allows the ATE to maintain its original memory size while still accessing all necessary test and repair data.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent extracts the function of storing large amounts of defect and repair information from the ATE itself and places it in an external memory device. This separation allows the ATE to remain cost-effective while the external memory provides the necessary storage capacity for comprehensive memory testing and repair operations.

Inventive Principle:
Principle #2Taking out (Extraction)

2Reliability

If multiple tests and repairs are performed due to insufficient ATE memory space, then the testing can be completed, but the test time increases

Engineering Contradiction:
Improvetesting completionVSAvoidtest time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary actions by storing all necessary defect information and repair information in the external memory before and during the testing process. This preparation ensures that when defects are detected, the repair information is already available in the external memory, allowing immediate repair operations without time-consuming repeated testing cycles.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent enables continuous testing and repair operations by maintaining all necessary information in the external memory throughout the test process. The ATE can continuously access defect locations and repair strategies without interruption, eliminating the need to suspend testing for memory management operations and maintaining uninterrupted productive action.

Inventive Principle:
Principle #20Continuity of useful action

3Productivity

If high-rate compression testing is used to work around limited ATE memory, then the test speed is improved, but the yield decreases due to failed repairs

Engineering Contradiction:
Improvetest speedVSAvoidyield
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The external memory acts as a mediator that preserves complete defect and repair information during high-rate compression testing. This intermediary storage ensures that even when testing proceeds at high speeds with compression techniques, no repair information is lost or corrupted, maintaining both the speed benefits and the reliability needed for successful repairs.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS11854642B2Memory test methods and related devices
Publication Date: 2023.12.26 CHANGXIN MEMORY TECH INC
  • US11854642B2 patent drawing
  • US11854642B2 patent drawing
  • US11854642B2 patent drawing

AI summary

A memory test method includes: testing a first memory to acquire defect information of the first memory; acquiring repair information of the first memory according to the defect information of the first memory; and storing the repair information of the first memory in a second memory. In the technical solutions provided in the embodiments of the present disclosure, other memories may be used to store the repair information of the currently tested memory, so that the storage space can be increased and the test efficiency can be improved.