External Quiesce Mechanism for Multi-Core SoC Error Containment
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Solution Overview
Problem
As multi-core SoCs scale larger, fatal error conditions on one core can affect a growing number of other cores, leading to increased system reboots and downtime, as there is no effective mechanism to gracefully quiesce an inoperative core without causing a cascade of errors or requiring a reboot of the entire system.
Innovation Solution
The implementation of an external quiesce mechanism allows an external entity to asynchronously quiesce a failing core by using a combination of firmware and hardware flows, enabling the core to be gracefully terminated and removed from the coherency network, even if it cannot execute instructions, thereby avoiding system-wide reboots.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If synchronous operations are used to take a core offline, then the core can be removed from service, but an inoperative core cannot perform such operations which may lead to OS errors and system reboots
Solution Approach 1:
The patent introduces an intermediary mechanism (external quiesce input signal and associated control logic) that mediates between the operating system's desire to take a core offline and the core's inability to execute synchronous operations. This intermediary allows the OS to initiate an asynchronous quiesce process that doesn't require the failing core to execute instructions, thereby resolving the contradiction between system reliability and ease of core management.
Solution Approach 2:
The patent implements preliminary action by having the operating system detect error conditions and initiate the quiesce process before the core completely fails. The OS sets error bits and triggers the asynchronous quiesce mechanism in advance, allowing for graceful core removal before catastrophic failure occurs, thus maintaining system stability while enabling core offline capability.
2Productivity
If more cores are added to increase processing capabilities, then economies of scale are achieved, but the blast radius of fatal errors increases affecting more cores
Solution Approach 1:
The patent applies segmentation by dividing the error containment boundary to the individual core level. Each core operates independently with its own error detection and quiesce mechanisms, allowing errors to be isolated to single cores rather than propagating across the entire multi-core system. This enables high productivity through multiple cores while minimizing error propagation impact.
Solution Approach 2:
The patent converts the potential harm of core failures into benefit by implementing error detection mechanisms that identify failing cores and trigger asynchronous quiesce processes. What would otherwise be catastrophic system-wide failures are transformed into isolated, containable events that allow the remaining cores to continue operating, thus turning the risk of multi-core errors into an opportunity for improved system resilience.
3Reliability
If the entire system is rebooted to handle fatal errors, then system stability is restored, but all processes running on the system are interrupted
Solution Approach 1:
The patent extracts the failing core from the system by implementing asynchronous quiesce mechanisms that remove individual problematic cores without affecting the rest of the multi-core system. The OS can detect errors, set error bits, and trigger quiesce processes that isolate and remove only the affected core, leaving other cores and their processes uninterrupted. This eliminates the need for full system reboots while maintaining system recoverability.
Data Source
AI summary
Disclosed are techniques for external quiesce of a core in a multi-core system. In some aspects, a method for external quiesce of a core in a multi-core system-on-chip (SoC), comprises, at control circuitry for the multi-core SoC, receiving an indication that a core in a multi-core SoC should be quiesced, determining that the core should be externally quiesced, and asserting an external quiesce request input into the core.