Fabric and Memory Controller Low Power State During Active Compute
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Solution Overview
Problem
Current computing devices face significant power consumption issues due to the lack of low power consumption state utilization in components like shared fabrics and memory controllers, even when processors are in active states, leading to increased overall power usage.
Innovation Solution
Introducing a new low power consumption state for System On Chip (SOC) components, where the memory controller and fabric can enter a low power state while the processor is active, by reducing operating clock frequency or modifying voltage, and utilizing local memory or cache hierarchies to minimize access to shared resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the processor enters low power states (C1-C6) to reduce power consumption, then power consumption is reduced, but system performance and functionality are degraded
Solution Approach 1:
The system segments power management into two independent domains: processor power states (C-states) and fabric/memory controller power states. This allows the processor to enter low power states while the fabric and memory controller maintain operational readiness, and vice versa, resolving the contradiction by enabling independent power optimization of each component without forcing the entire system into a uniform power state.
Solution Approach 2:
The patent implements dynamic power state transitions for fabric and memory controller based on real-time processor activity monitoring. When the processor is active, the fabric/memory controller can dynamically switch to low power states if idle; when the processor enters low power states, the fabric/memory controller can dynamically activate to maintain system responsiveness. This dynamic adaptation resolves the contradiction by optimizing power consumption without permanently sacrificing performance.
2Speed
If the fabric and memory controller remain in active state to support processor operations, then system responsiveness is maintained, but power consumption increases
Solution Approach 1:
The fabric and memory controller implement self-service power management by autonomously monitoring their own activity levels and processor state, and automatically transitioning to low power states when idle conditions are detected. This eliminates the need for continuous high-power operation while maintaining system responsiveness, as the components can quickly reactivate when needed without manual intervention or complex system-wide coordination.
Solution Approach 2:
The system implements feedback mechanisms where the processor communicates its operational state to the fabric and memory controller, which then adjust their power states accordingly. When the processor indicates active operation, the fabric/memory controller receives feedback to maintain or enter active state; when the processor enters low power states, feedback triggers the fabric/memory controller to transition to low power states. This feedback loop resolves the contradiction by aligning power consumption with actual system demand.
3Use of energy by moving object
If local memory or cache hierarchies are utilized to minimize access to shared resources, then power consumption is reduced, but memory access capacity is constrained
Solution Approach 1:
The system applies local quality by implementing cache memory hierarchies (L1, L2, L3 caches) with different characteristics optimized for specific access patterns. Frequently accessed data resides in smaller, faster, lower-power local caches, while less frequently accessed data remains in larger, slower, higher-capacity shared memory. This hierarchical approach resolves the contradiction by providing both low-power local access and high-capacity shared access, with the system automatically selecting the appropriate memory level based on access frequency and size requirements.
Data Source
AI summary
Methods and apparatus to permit a system low power consumption state when CPU (Central Processing Unit) or generically any compute element is active are described. In an embodiment, a fabric and a memory controller are caused to enter a low power consumption state at least partially in response to a determination that the fabric and the memory controller are idle. The entry into the low power consumption state occurs while a compute element, coupled to the fabric and the memory controller, is in an active state. Other embodiments are also disclosed and claimed.