Susbset Functionality Use TRIZ Cases

An adjustable VDDQ supply lowers voltage in unterminated memory transfers to cut AC power while preserving terminated-mode signaling.

FRAM-based nonvolatile logic stores machine state before power loss, enabling zero-leakage sleep and fast resume under inconsistent supply.

FRAM-based nonvolatile logic captures SoC state before power-off, eliminating standby leakage and enabling instant-on recovery.

Adaptive power-on reset timing matches supply-voltage rise time to cut standby delay and power use while keeping internal circuits reliable.

Self-capacitance switching lets an RF antenna distinguish touch states without calibration, improving recognition and lowering power use.

An address monitoring circuit detects access states of cache memory and input/output interfaces to enable selective power gating.

Checksum-based self-refresh allows system on chip to shut down wake-up power island, reducing sleep power below 10 mW and accelerating resume time.

Controller adjusts processor clock and voltage to switch between symmetric and asymmetric modes, eliminating duplicate hardware complexity.

Shared memory objects enable virtual machines to coordinate power management decisions directly with hardware resources.

A vehicle information display apparatus switches to a power-saving mode upon trigger detection to prepare system initialization before engine start.

A control unit switches specific display areas between operable and non-operable states using proximity and load sensors.

A data processing system calculates hardware standby times against break-even thresholds to manage power supply transitions.

Classifying processes as exempt, suspendable, or throttleable optimizes power consumption in connected standby mode.

Event sensing panels adjust sensor density dynamically to optimize input resolution and power usage.

Segmented touch panel electrodes enable gesture detection in sleep mode, reducing power consumption by avoiding continuous mutual-capacitive sensing.

A control module stores and retrieves configuration information using a hardware interrupt signal to manage peripheral unit state transitions.

A management module places unused virtual switches and physical NICs into standby mode to conserve resources.

Full handshake clock gating disables unused IP blocks to lower power consumption and prevent overheating in high-density SoCs.

Segmenting voice commands allows a secondary processor to update displays and handle interactions without waking the main CPU, reducing power consumption.

Wake-up bus synchronizes parallel power devices via AND logic, maintaining high efficiency during light load conditions.

A printer controller adjusts standby duration based on job type to balance power consumption with user wait times.

A screen control section generates a display screen matching the logged-in user after switching from power saving mode to normal mode.

Restricting volatile memory refresh operations during instruction fetching prevents data interference, ensuring reliable reset and power cutoff transitions.

A secondary processor segments voice commands to allow user interactions during sleep mode, reducing power consumption by avoiding full wake-ups.

Motion sensor detects vibration frequency and acceleration to manage backlight power state.

First terminal relays external network data to a second terminal while in sleep mode, enabling application launch without base unit power.

Dynamic cooling throttling during NVDIMM data backup operations preserves internal UPS power for extended write durations.

A memory management unit partitions memory into collapsible and non-collapsible regions to allocate thread tasks.

An image forming apparatus adjusts initialization processing based on the selected initial screen to reduce unnecessary energization.

Physical interface reconfigures between low-power and high-speed modes using code words within a common voltage range.

A storage device sleep mode detection method transmits a Devslp command to enable low power state entry.

A processor mailbox interface stores core context information to enable independent voltage and frequency control across multiple cores.

A protocol analyzer detects non-signals returned via the data line from a storage device.

Grouping sensing and conversion units allows selective powering down to reduce consumption while maintaining touch sensitivity.

A rotatable display unit adjusts power saving thresholds based on orientation to extend usable time during self-shooting preparation.

Domain master node synchronizes ordinary nodes into energy-saving modes based on local traffic patterns.

A user interface manages power states by coordinating low power entries across data and clock lanes to reduce energy consumption.

A switching controller transitions the device from low power to normal status when a signal detector identifies an external connection.

Dynamic infrared light emission reduces power consumption and extends lifespan while maintaining detection accuracy.

Control circuitry detects identical micro-operations across processing lanes to share results, suppressing redundant execution to lower energy consumption.

Media guidance application delays power management until media asset end point, preventing disruptions to engaged users.

A monitoring apparatus coordinates IT device layer power states with infrastructure cooling deployment.

A memory control chip stops internal clock signals to inactive circuit groups to reduce power consumption.

A sub controller circuit bridges networks to handle proxy responses, avoiding route instability and reducing device costs.

An in-memory power manager controls DDR memory modules by enabling direct transitions between fine-grained power states.

Compiler driven power gating segments processor cores to power down idle functional units, reducing leakage current while maintaining execution speed.

A display driver IC uses a booster and power level adjustor to manage internal voltage levels during mode transitions.

Memory controller and fabric enter low power states while processor remains active, reducing system energy usage.

Segmented graphics cores use dynamic power gating and independent clock management to balance processing speed against power consumption.