Reconfigurable Graphics Processor Power Gating

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Graphics processors face challenges in maximizing performance while operating within different power consumption modes, as existing technologies struggle to efficiently manage power gating and frequency scaling to balance performance and power efficiency.

Innovation Solution

The implementation of dynamic power gating mechanisms that automatically reconfigure graphics processing cores by activating or deactivating subslices, using power sharing and independent clock management for scalable and non-scalable portions, to optimize performance within varying power budgets.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If dynamic power gating is implemented to activate or deactivate subslices, then power consumption is reduced, but device complexity increases

Engineering Contradiction:
Improvepower consumptionVSAvoiddevice complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The graphics processing core is divided into multiple independently power-gatable subslices. Each subslice can be individually activated or deactivated based on power budget requirements, allowing fine-grained power control without requiring complete system shutdown or complex global power management

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The power gating mechanism dynamically adjusts the active subslice configuration based on real-time power budget conditions. The system can transition between different numbers of active subslices (e.g., from all subslices active to fewer subslices active) to optimize power consumption while maintaining operational flexibility

Inventive Principle:
Principle #15Dynamics

2Speed

If clock frequency is increased to improve performance, then processing speed increases, but power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The system dynamically changes the clock frequency parameter based on the number of active subslices and power budget conditions. When fewer subslices are active, the clock frequency can be increased to maintain overall performance while reducing total power consumption, creating an optimized balance between speed and energy usage

Inventive Principle:
Principle #35Parameter changes

3Productivity

If more subslices are activated to increase performance, then processing capability improves, but power consumption increases

Engineering Contradiction:
Improveprocessing capabilityVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSUse of energy by moving object

Solution Approach 1:

The graphics core is segmented into multiple subslices that can be independently controlled. This allows the system to activate only the necessary number of subslices required for current workload demands, avoiding the power waste of keeping all subslices active when full processing capability is not needed

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system activates only the partial number of subslices necessary to meet current performance requirements rather than always activating all available subslices. This partial activation strategy reduces power consumption while maintaining sufficient processing capability for the given workload

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS10242652B2Reconfigurable graphics processor for performance improvement
Publication Date: 2019.03.26 INTEL CORP
  • US10242652B2 patent drawing
  • US10242652B2 patent drawing
  • US10242652B2 patent drawing

AI summary

Power gating a portion of a graphics processor may be used to improve performance or to achieve a power budget. A processor granularity, such as a slice or subslice, may be gated.