Power-On Reset Circuit Timing for Faster Semiconductor Startup
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Solution Overview
Problem
The rise time of supply voltage to rated voltage varies, leading to delayed microcomputer operation and increased power consumption due to inefficient voltage monitoring timer circuits in existing semiconductor devices.
Innovation Solution
A semiconductor device with a POR circuit, AND gate, flip flop, counter, and storage section that adjusts the timing of internal reset signal generation to match the rise time of supply voltage, allowing for flexible reset timing and reduced standby time, thereby minimizing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a voltage monitoring timer circuit is used to reset the microcomputer after supply voltage reaches threshold voltage, then the microcomputer operation reliability is improved, but the standby time is increased and power consumption is increased
Solution Approach 1:
The patent applies dynamics by making the reset release timing adaptable to different supply voltage rise times. The voltage monitoring timer circuit is configured to release the reset signal at an appropriate timing that matches the actual rise time characteristics of the supply voltage, rather than using a fixed predetermined time. This dynamic adjustment eliminates unnecessary standby time while ensuring the microcomputer operates reliably, thereby resolving the contradiction between reliability and time loss.
2Reliability
If a voltage monitoring timer circuit with predetermined standby time is used, then the microcomputer starts operation after voltage stabilization, but the power consumption is increased due to wasteful standby time
Solution Approach 1:
The patent applies parameter changes by adjusting the reset release timing parameter based on the actual supply voltage rise time characteristics. Instead of using a fixed predetermined standby time, the system dynamically sets the release timing to match the actual voltage stabilization time. This parameter optimization ensures voltage stabilization is achieved while minimizing unnecessary standby time and reducing power consumption during the startup phase.
3Device complexity
If the reset release timing is set to a fixed predetermined time, then the circuit design is simplified, but the microcomputer operation is delayed when rise time is shorter than standby time
Solution Approach 1:
The patent applies dynamics by implementing an adjustable reset release timing mechanism that adapts to different supply voltage rise time characteristics. The voltage monitoring timer circuit can be configured to release the reset signal at optimal timing based on actual operating conditions, rather than using a fixed predetermined time. This dynamic approach accelerates microcomputer startup when rise time is short while maintaining circuit design feasibility through standardized timer components with adjustable parameters.
Data Source
AI summary
A semiconductor device which makes it possible to reduce a wasteful standby time at power-on is provided. In this semiconductor device, a reset of an internal circuit is canceled as described below. When a data signal stored in a storage section is at “0,” the reset is canceled by bringing an internal reset signal to the “H” level when a relatively short time has passed after the rising edge of a power on reset signal. When the data signal is at “1,” the reset is canceled by bringing the internal reset signal to the “H” level when a relatively long time has passed after the rising edge of the power on reset signal. Therefore, a wasteful standby time at power-on can be reduced by writing the data signal logically equivalent to the rise time of supply voltage to the storage section.