Nonvolatile Logic Arrays for Intermittent Power State Retention
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information, allowing complete power removal without data loss, with NVL arrays dispersed throughout the logic cloud and controlled by a central NVL controller for efficient state retention and restoration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially requiring continuous power
Solution Approach 1:
The patent changes the fundamental parameter of state storage from volatile (requiring continuous power) to non-volatile (retaining state without power). By using ferroelectric RAM (FRAM) with hysteresis-based polarization states instead of traditional CMOS latches, the system achieves zero leakage current in standby mode while maintaining data retention through the non-volatile nature of ferroelectric material polarization.
2Speed
If traditional volatile memory is used, then rapid access speed is achieved, but continuous power is required causing leakage current
Solution Approach 1:
The patent segments the memory system into non-volatile FRAM for state retention and volatile CMOS logic for processing. The FRAM stores state information without power while the CMOS logic operates at full speed when powered, allowing the system to achieve both energy efficiency and processing performance through functional segmentation.
3Adaptability or versatility
If energy harvesting is used to power portable devices, then power independence is improved, but the small amount of harvested power is insufficient for continuous operation
Solution Approach 1:
The patent enables periodic operation where the device operates when harvested power is available and enters a true power-off state when it is not. The non-volatile FRAM preserves state information across power cycles, allowing the device to resume operation later without data loss, making periodic harvesting-synchronized operation feasible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables zero-leakage operation in sleep mode and rapid system state restoration, reducing power consumption and eliminating the need for constant power sources, ideal for energy harvesting applications and handheld devices with limited resources.
Implementation Method 1
Implementing non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) to store state information
Data Source
AI summary
Input power quality for a processing device is sensed. In response to detection of poor power quality, input power is disconnected, and the processing device backs up its machine state in non-volatile logic element arrays using available stored charge. When power is restored, the stored machine state is restored from the non-volatile logic element arrays to the volatile logic elements whereby the processing device resumes its process from the state immediately prior to power loss allowing seamless processing across intermittent power supply.