Memory Interface Voltage Switching for Low-Power Unterminated Modes

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Solution Overview

Problem

Current memory interfaces, such as LPDDR4, face inefficiencies in power consumption due to constant voltage supply across terminated and unterminated modes, leading to increased AC power consumption in unterminated modes.

Innovation Solution

Implementing an adjustable power supply that lowers the VDDQ voltage in unterminated mode, allowing the memory interface to switch between terminated and unterminated modes by adjusting the power supply voltage, thereby reducing AC power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the memory interface uses constant VDDQ voltage supply across both terminated and unterminated modes, then the power supply circuit is simple, but the AC power consumption increases significantly in unterminated mode

Engineering Contradiction:
Improvepower supply circuit complexityVSAvoidAC power consumption
Core Design Contradiction:
Device complexityVSLoss of energy

Solution Approach 1:

The power supply circuit dynamically adjusts the VDDQ voltage level based on the transmission mode. In terminated mode, a higher voltage (e.g., 1.1V) is supplied to ensure proper signal integrity and impedance matching. In unterminated mode, the voltage is reduced (e.g., to 0.8V or lower) to decrease AC power consumption, since the full voltage swing is not needed when termination resistance is not active.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The invention changes the voltage parameter of the power supply based on operational conditions. By detecting whether the interface is in terminated or unterminated mode, the system modifies the VDDQ voltage parameter accordingly, optimizing the balance between power consumption and signal quality for each mode.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If the memory interface uses higher voltage during terminated mode to maintain signal integrity, then the signal quality is improved, but the power consumption increases when not needed

Engineering Contradiction:
Improvesignal integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The system dynamically adapts the voltage level to the current operational mode. During terminated mode, higher voltage ensures proper signal integrity and impedance matching. During unterminated mode, the voltage is lowered since the full swing is not required, thereby reducing unnecessary power consumption while maintaining adequate signal quality for the reduced-speed operation.

Inventive Principle:
Principle #15Dynamics

3Speed

If the memory interface operates in unterminated mode with full voltage swing, then the data transmission speed can be reduced, but the AC power consumption increases four times compared to terminated mode

Engineering Contradiction:
Improvedata transmission speedVSAvoidAC power consumption
Core Design Contradiction:
SpeedVSLoss of energy

Solution Approach 1:

The power supply dynamically adjusts voltage based on transmission mode and speed requirements. In unterminated mode operating at reduced speeds, the system lowers the VDDQ voltage to minimize AC power consumption, which is proportional to the square of the voltage swing. This dynamic adjustment reduces power consumption by approximately four times compared to maintaining full voltage during unterminated operation.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10613613B2Memory interface with adjustable voltage and termination and methods of use
Publication Date: 2020.04.07 QUALCOMM INC
  • US10613613B2 patent drawing
  • US10613613B2 patent drawing
  • US10613613B2 patent drawing

AI summary

A memory interface includes: a pull-up device and a pull-down device, wherein the pull-up device couples between a power rail and a data line, and wherein the pull-down device couples between the data line and ground; and a power supply configured to supply a first power supply voltage to the power rail during a terminated data transmission mode in which a receiving memory interface coupled to the data line has an active on-die termination, and wherein the power supply is further configured to supply a second power supply voltage to the power rail during an unterminated data transmission mode in which the on-die termination does not load the data line, the second power supply voltage being less than the first power supply voltage.