FRAM Nonvolatile Logic Backup for Zero-Leakage SoC Standby
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Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM) allows for zero leakage in sleep mode and instant-on capability, enabling state retention without continuous power, by dispersing NVL arrays throughout the logic cloud and utilizing a central NVL controller for state management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If shadow latch is used to retain state information during standby power mode, then data retention is improved, but leakage current is reduced only partially and additional power supply circuitry is required
Solution Approach 1:
The patent extracts the state retention function from the traditional shadow latch circuit and relocates it to a separate non-volatile memory array. This allows the main logic array to be completely powered down without requiring any retention circuitry to remain active, eliminating both leakage current and the need for separate always-on power supplies.
Solution Approach 2:
The patent introduces a non-volatile memory array as an intermediary between the logic array and state retention requirements. This intermediary stores the state information when power is removed and can restore it when power is reapplied, eliminating the need for continuous power to retain state.
2Loss of energy
If multi-threshold CMOS technology is used to reduce leakage current, then power consumption is reduced, but device complexity increases due to multiple transistor types
Solution Approach 1:
The patent segments the system into two distinct functional areas: a volatile logic array for active computation and a non-volatile memory array for state retention. This segmentation allows each area to be optimized independently - the logic array uses standard transistors for high-speed operation while the non-volatile array handles retention, avoiding the need for complex multi-threshold transistors throughout the entire device.
3Reliability
If state information is retained in shadow latch during standby mode, then functionality is preserved, but boot time is extended due to power management overhead
Solution Approach 1:
The patent performs preliminary action by storing the complete state of the logic array in the non-volatile memory array before power is removed. This preliminary state capture allows the system to resume operation immediately upon power restoration without needing to reinitialize or reboot, significantly reducing boot time while preserving functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables devices to power down completely without losing functionality, reducing energy consumption and boot time, making it suitable for energy harvesting applications and improving battery life in portable devices.
Implementation Method 1
non-volatile logic (NVL) within System on Chip (SoC) using ferroelectric random access memory (FRAM)
Data Source
AI summary
A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.