Face-to-Face Compound Semiconductor Layout for Low-Loss Gate Contacts
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Solution Overview
Problem
Existing compound semiconductor devices face limitations in achieving high power density and frequency operation due to constraints in gate electrical contact design and packaging, leading to parasitic losses and reduced reliability.
Innovation Solution
Coupling first and second compound semiconductor devices in a face-to-face arrangement with hermetically sealed cavities for gate electrical contacts, minimizing dielectric material presence, and utilizing double-sided cooling through silicon carbide substrates to enhance power density and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If compound semiconductor devices are designed for high power density operation, then power output increases, but parasitic losses increase and reliability decreases
Solution Approach 1:
The device is divided into two separate compound semiconductor devices coupled face-to-face, with each device having its own gate electrical contact. This segmentation allows the gate contacts to be isolated in separate hermetically sealed cavities, reducing parasitic interactions while maintaining high power density operation.
Solution Approach 2:
The gate electrical contacts are extracted from the main device structure and placed in separate hermetically sealed cavities. This extraction isolates the gate contacts from contaminants and reduces parasitic losses, improving reliability while allowing the main devices to operate at high power density.
2Power
If gate electrical contacts are exposed to improve electrical connection, then electrical conductivity increases, but contamination increases and reliability decreases
Solution Approach 1:
The gate electrical contacts are enclosed in hermetically sealed cavities that create a protected environment. This inert environment prevents contaminants from reaching the gate contacts while maintaining optimal electrical connection, thus improving reliability without sacrificing conductivity.
3Power
If dielectric material is used to insulate gate electrical contacts, then electrical isolation improves, but parasitic losses increase
Solution Approach 1:
The gate electrical contacts are extracted and placed in separate hermetically sealed cavities, eliminating the need for dielectric materials between them. This extraction provides electrical isolation through physical separation and hermetic sealing while minimizing parasitic losses by removing dielectric materials that would otherwise be present.
4Reliability
If packaging is increased to protect gate electrical contacts, then reliability improves, but device complexity increases
Solution Approach 1:
The hermetic sealing function and the gate contact protection function are merged into a single integrated structure. The cavities that contain the gate contacts also provide the hermetic seal, eliminating the need for separate packaging layers and reducing overall device complexity while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The face-to-face arrangement increases power density to at least 8 W/mm gate width at frequencies up to 30 GHz, reduces parasitic losses, and enhances reliability by protecting gate electrical contacts from contaminants, while minimizing packaging needs.
Implementation Method 1
double-sided cooling through silicon carbide substrates
Data Source
AI summary
In one or more implementations, a semiconductor device can include a first compound semiconductor device coupled to a second compound semiconductor device coupled in a face-to-face arrangement. The first compound semiconductor device can be coupled to the second compound semiconductor device such that a cavity is formed that includes a first gate electrical contact of the first compound semiconductor device and a second gate electrical contact of the second compound semiconductor device. A gap can be present between the first gate electrical contact and the second gate electrical contact.