Failure Detector Circuit Reduces Quiescent Current via Periodic Sampling
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Solution Overview
Problem
Existing power supply circuits face efficiency constraints due to high quiescent current consumption by control chips used for monitoring and protection, limiting the improvement of operating efficiency.
Innovation Solution
A failure detector circuit comprising an enabling signal generator, a comparator circuit, and a delay circuit that generates a periodic enabling signal, compares output signals from a protected circuit with reference signals, and provides a delay signal only during a specific enable time, reducing continuous operation and thus minimizing quiescent current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a control chip is applied to monitor voltage, current, temperature or other parameters of the protected circuit, then circuit protection capability is improved, but quiescent current consumption increases
Solution Approach 1:
The patent implements periodic sampling of circuit parameters instead of continuous monitoring. The enabling signal generator produces periodic enabling signals that activate the comparator circuit at specific intervals, allowing the system to detect failures while consuming minimal quiescent current during non-active periods.
Solution Approach 2:
The system dynamically switches between active monitoring and standby states. The comparator circuit is enabled only during specific time windows when the enabling signal is active, and disabled during other periods, creating a dynamic operation mode that reduces average power consumption while maintaining protection capability.
2Reliability
If the comparator circuit operates continuously to detect failures, then detection reliability is improved, but quiescent current consumption increases
Solution Approach 1:
The comparator circuit operates periodically based on the enabling signal rather than continuously. It compares the output signal with the reference signal only during enabled time windows, achieving reliable failure detection while minimizing power consumption during disabled periods.
Solution Approach 2:
The system uses a delay circuit that generates a delay signal based on the comparative result signal. This preliminary action allows the system to detect failures and initiate protection responses with appropriate timing, ensuring reliable detection without requiring continuous comparator operation.
3Speed
If the operating cycle is shortened to improve response speed, then detection speed is improved, but the delay period becomes insufficient for accurate detection
Solution Approach 1:
The system uses periodic enabling signals with optimized duty cycles to balance response speed and detection accuracy. The period and width of enabling signals are designed to provide sufficient sampling intervals for accurate detection while maintaining fast response capability.
Solution Approach 2:
The delay circuit acts as an intermediary between the comparator circuit and the protection logic. It processes the comparative result signal with an appropriate delay period, ensuring that detection decisions are made with sufficient time for accurate comparison while maintaining overall system response speed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution significantly reduces quiescent current consumption by enabling the failure detector circuit only during a portion of the operating cycle, improving the overall efficiency of the power supply circuit to 1% of the prior art's consumption while maintaining effective failure detection.
Implementation Method 1
a comparator circuit, having an enabling terminal, two input terminals and a output terminal, wherein a enabling terminal receives the enabling signal, and wherein the two input terminals respectively receive an output signal from a protected circuit and a reference signal, and wherein the output terminal generates a comparative result signal according to the enabling signal, the output signal and the reference signal
Implementation Method 2
a delay circuit, receiving and detecting the comparative result signal for a given delay period, generating a delay signal according to the comparative result signal, wherein the given delay period is larger than the operating cycle
Data Source
AI summary
A failure detector circuit for detecting status of a protected circuit, the failure detector circuit having an operating cycle, has an enabling signal generator, a comparator circuit, a delay circuit. The enabling signal generator enables the comparator for an enable time in each operating cycle. The comparator circuit compares an output of the protected circuit with a reference signal. The delay circuit receives an output signal of the comparator to decide whether a failure occurred within a give delay time.