Fan-Out Chip Package Structure for Dense 3D Die Stacking
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high density and functionality while maintaining efficient manufacturing processes, particularly in the context of 3D packaging and 3D-IC devices.
Innovation Solution
A method for forming a chip package with a fan-out feature involving a redistribution structure over a carrier substrate, including insulating and conductive layers, conductive pillars, and interposer substrates, which allows for the stacking and connection of semiconductor dies and device elements, and includes a protective layer to secure and protect the components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If smaller package structures are developed to reduce area and height, then manufacturing efficiency is improved and costs are lowered, but achieving high density and functionality becomes more challenging
Solution Approach 1:
The patent implements a stacked package structure where multiple semiconductor dies are vertically arranged and interconnected through conductive vias and redistribution layers. This nesting approach allows multiple functional layers to be integrated within a compact footprint, achieving high density while maintaining manufacturing efficiency through standardized stacking processes
Solution Approach 2:
The patent transitions from planar packaging to three-dimensional stacking by arranging semiconductor dies in the vertical dimension. This dimensional change enables higher device density without increasing package area, and allows interconnections to be established through vertical vias rather than lateral routing, simplifying the packaging complexity
2Quantity of substance
If 3D packaging technologies are implemented to improve density, then functionality is enhanced, but manufacturing challenges increase
Solution Approach 1:
The patent performs preliminary alignment and bonding of semiconductor dies to a carrier substrate before subsequent processing steps. This preliminary action ensures precise positioning and stable interconnections are established early in the manufacturing process, facilitating later steps such as via formation and redistribution layer deposition without compromising manufacturing ease
Solution Approach 2:
The patent divides the 3D package structure into discrete manufacturable layers including semiconductor dies, conductive vias, redistribution layers, and encapsulation layers. Each layer can be processed and quality-checked independently, making the complex 3D packaging manufacturing process more manageable and easier to execute
3Reliability
If conductive features and protective layers are added to protect semiconductor devices, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple protective and interconnect functions into integrated structures. For example, redistribution layers serve both as electrical interconnections between dies and as protective barriers, while encapsulation layers simultaneously protect multiple dies and provide mechanical support. This merging reduces the number of separate components needed, lowering structural complexity while maintaining reliability
Data Source
AI summary
A package structure is provided, which includes a redistribution structure, an interposer substrate disposed over the redistribution structure, a first semiconductor die disposed between the redistribution structure and the interposer substrate, a second semiconductor die partially overlapping the first semiconductor die in a direction perpendicular to a surface of the redistribution structure, and a first protective layer surrounding the first semiconductor die.