Fan-Out Interconnect Structure for Semiconductor Substrate I/O Density Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor devices face high manufacturing costs and reduced flexibility due to the need for high I/O density layouts in substrates, which complicates the routing of trace lines and increases the cost of substrates.
Innovation Solution
The method involves forming an extended semiconductor device with a fan-out interconnect structure that reduces the I/O density of the substrate, allowing for a more relaxed layout design rule, which decreases the cost and complexity of substrate manufacturing by spreading out the interconnects and using a common substrate for various semiconductor dies with different I/O layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high I/O density layout is used in substrate to meet semiconductor die requirements, then electrical interconnection is achieved, but substrate complexity and manufacturing cost increase
Solution Approach 1:
The substrate is divided into a first substrate region and a second substrate region with different I/O densities. The first region (under the die) has high I/O density to provide electrical interconnection, while the second region (peripheral area) has low I/O density to reduce complexity and manufacturing cost. This spatial segmentation allows each region to be optimized for its specific function.
2Area of moving object
If minimum pitch is used for contact pads to maximize I/O density, then die size is minimized, but substrate layout flexibility is reduced
Solution Approach 1:
Different pitch requirements are applied to different regions of the substrate. The first substrate region uses minimum pitch to maximize I/O density and minimize die size, while the second substrate region uses relaxed pitch to provide layout flexibility. This local differentiation of quality parameters resolves the contradiction between minimizing die size and maintaining layout flexibility.
3Reliability
If high I/O density is maintained throughout substrate to ensure electrical connection, then interconnect reliability is improved, but manufacturing cost increases
Solution Approach 1:
The substrate manufacturing process is segmented into different regions with different I/O density requirements. The first region maintains high I/O density for reliable electrical connection, while the second region reduces I/O density to lower manufacturing cost. This segmentation allows cost reduction in non-critical areas while preserving reliability in critical interconnection areas.
Data Source
AI summary
A semiconductor device has a semiconductor wafer with a plurality of semiconductor die. Contact pads are formed on a surface of the semiconductor die. The semiconductor die are separated to form a peripheral region around the semiconductor die. An encapsulant or insulating material is deposited in the peripheral region around the semiconductor die. An interconnect structure is formed over the semiconductor die and insulating material. The interconnect structure has an I/O density less than an I/O density of the contact pads on the semiconductor die. A substrate has an I/O density consistent with the I/O density of the interconnect structure. The semiconductor die is mounted to the substrate with the interconnect structure electrically connecting the contact pads of the semiconductor die to the first conductive layer of the substrate. A plurality of semiconductor die each with the interconnect structure can be mounted over the substrate.