Fan-Out Package Reduces Impedance in Semiconductor Storage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Impedance mismatch in the electrical path between a processor and a controller chip in semiconductor storage devices leads to deteriorated signal quality, particularly at high speeds, due to increased parasitic capacitance in certain portions of the electrical path.
Innovation Solution
The design includes bumps that are strategically positioned directly below the memory controller, with a cross-sectional area less than or equal to the terminals they connect, reducing the length and impedance of the electrical path, and using a fan-out package structure to minimize parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the electrical path between processor and controller chip is extended to accommodate more components, then device functionality is improved, but parasitic capacitance increases causing impedance mismatch and signal quality deterioration
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement to a three-dimensional stacked configuration, placing the controller chip vertically above the processor through multiple packaging layers. This spatial reorganization shortens the electrical path length while maintaining all necessary connection points, thereby reducing parasitic capacitance without compromising device functionality.
Solution Approach 2:
The patent implements a nested packaging structure where the controller chip is embedded within the package substrate above the processor, with multiple interconnection layers nested between them. This nested arrangement allows dense integration of components while minimizing the horizontal distance between electrical connections, reducing parasitic effects.
2Ease of manufacture
If solder balls are used for connecting processor and controller chip, then ease of manufacture is improved, but electrical path length increases causing impedance mismatch
Solution Approach 1:
The patent divides the electrical connection path into multiple segmented conductors distributed across different packaging layers, rather than using a single long solder ball path. Each segment is optimized to be short, and the segments are connected through vertical vias and horizontal traces in the package substrate, collectively achieving a shorter total electrical path while maintaining manufacturing simplicity.
3Reliability
If impedance matching is improved by shortening electrical paths, then signal quality is improved, but device complexity increases
Solution Approach 1:
The package substrate serves multiple functions simultaneously: it provides mechanical support for stacking, creates vertical electrical connections through vias, provides horizontal routing paths, and enables impedance control through its layered structure. This multi-functionality achieves signal quality improvement without proportionally increasing device complexity, as a single component (the package substrate) handles multiple design requirements.
Data Source
AI summary
An electronic apparatus includes first and second packages. The first package includes a first semiconductor chip between opposing first and second surfaces of the first package, a plurality of terminals on the first semiconductor chip facing a first direction that is perpendicular to the first and second surface, the terminals including first input/output terminals and a second input/output terminal, and a plurality of bumps that are electrically connected to the plurality of first input/output terminals at positions that are directly below the first semiconductor chip in the first direction. The second package includes a second semiconductor chip provided on the second surface of the first package, a wire that electrically connects the second semiconductor chip to a conductor that is electrically connected to the second input/output terminal, and coating resin that covers the second surface of the first package, the second semiconductor chip and the wire.